HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 36

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 50.
Default values are highlighted.
Table 51.
Default values are highlighted.
ADC1413D_SER
Product data sheet
Bit
0
Bit
7
6
5 to 4
3
2
1
0
Symbol
LANE_PD
Symbol
-
SCR_IN_MODE
LANE_MODE[1:0]
-
LANE_POL
LANE_CLK_POS_EDGE R/W
LANE_PD
Lane0_0_Ctrl (address 0870h)
Lane1_0_Ctrl (address 0871h)
R/W
R/W
R/W
-
R/W
R/W
Access
Access
-
All information provided in this document is subject to legal disclaimers.
…continued
Value
0
1
Value
0
0 (reset)
1
00 (reset)
01
10
11
0
0
1
0
1
0
1
Rev. 5 — 9 February 2011
defines lane polarity:
Description
lane power-down control:
Description
not used
defines the input type for scrambler and 8-bit/10-bit units:
defines output type of lane output unit:
not used
defines lane clock polarity:
lane power-down control:
lane is operational
lane is in Power-down mode
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE[1:0]”
(Ser_PRBS_Ctrl register)
normal mode: lane output is the 8-bit/10-bit output unit
constant mode: lane output is set to a constant (0x0)
toggle mode: lane output is toggling between 0x0 and 0x1
PRBS mode: lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
lane polarity is normal
lane polarity is inverted
lane clock provided to the serializer is active on positive
edge
lane clock provided to the serializer is active on negative edge
lane is operational
lane is in Power-down mode
Dual 14-bit ADC; serial JESD204A interface
ADC1413D series
© NXP B.V. 2011. All rights reserved.
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