HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 19

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
ADC1413D_SER
Product data sheet
11.2.3 Common-mode output voltage (V
11.2.4 Biasing
11.3.1 Drive modes
11.3 Clock input
An 0.1 F filter capacitor should be connected between pins VCMA and VCMB and
ground to ensure a low-noise common-mode output voltage. When AC-coupled, these
pins can be used to set the common-mode reference for the analog inputs, for instance
via a transformer middle point.
The common-mode input voltage, V
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
The ADC1413D can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin
CLKM (pin CLKP should be connected to ground via a capacitor).
Fig 15. Reference equivalent schematic
Fig 16. LVCMOS single-ended clock input
a. Rising edge LVCMOS
0.1 μF
VCMA
VCMB
clock input
1.5 V
LVCMOS
All information provided in this document is subject to legal disclaimers.
PACKAGE
Rev. 5 — 9 February 2011
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CLKM
CLKP
ESD
I(cm)
PARASITICS
O(cm)
, at the inputs to the sample-and-hold stage
Dual 14-bit ADC; serial JESD204A interface
)
b. Falling edge LVCMOS
ADC1413D series
COMMON MODE
REFERENCE
clock input
LVCMOS
ADC CORE
© NXP B.V. 2011. All rights reserved.
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CLKM
CLKP
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