HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 13

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
ADC1413D_SER
Product data sheet
10.4 SPI timing
Table 8.
[1]
Symbol
t
t
t
t
t
f
w(SCLK)
w(SCLKH)
w(SCLKL)
su
h
clk(max)
Fig 5.
Typical values measured at V
across the full temperature range T
INBP)  V
unless otherwise specified.
SPI timing
SCLK
SPI timing characteristics
SDIO
I
CS
(INAM,INBM) = 1 dBFS; internal reference mode; 100  differential applied to serial outputs;
Parameter
SCLK pulse width
SCLK HIGH pulse
width
SCLK LOW pulse
width
set-up time
hold time
maximum clock
frequency
All information provided in this document is subject to legal disclaimers.
t
su
R/W
Rev. 5 — 9 February 2011
DDA
W1
t
h
t
= 3 V, V
su
amb
W0
t
= 40 C to +85 C at V
[1]
w(SCLK)
Conditions
data to SCLKH
CS to SCLKH
data to SCLKH
CS to SCLKH
DDD
= 1.8 V, T
A12
Dual 14-bit ADC; serial JESD204A interface
amb
A11
t
w(SCLKL)
= 25 C. Minimum and maximum values are
ADC1413D series
t
w(SCLKH)
DDA
Min
-
-
-
-
-
-
-
-
D2
= 3 V, V
D1
DDD
Typ
40
16
16
5
5
2
2
25
= 1.8 V; V
D0
© NXP B.V. 2011. All rights reserved.
t
h
005aaa065
Max
-
-
-
-
-
-
-
-
I
(INAP,
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
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