HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 14

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
11. Application information
ADC1413D_SER
Product data sheet
11.1.1 Input stage description
11.1 Analog inputs
The analog input of the ADC1413D supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
Figure 6
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Fig 6.
shows the equivalent circuit of the sample-and-hold input stage, including
Input sampling circuit
I(cm)
INAM
INBM
INAP
INBP
) on pins INxP and INxM set to 0.5V
All information provided in this document is subject to legal disclaimers.
1, 14
2, 13
Rev. 5 — 9 February 2011
package
ESD
Dual 14-bit ADC; serial JESD204A interface
Section 11.2
parasitics
DDA
ADC1413D series
.
R on = 15 Ω
R on = 15 Ω
internal
internal
and
switch
switch
clock
clock
Table
4 pF
4 pF
C s
C s
21).
005aaa069
© NXP B.V. 2011. All rights reserved.
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