DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 60

IC ETH TXRX T1/E1/J1 256-BGA

DS33R11+

Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS33R11+

Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Table 9-6. MAC Control Registers
Table 9-7. MAC Status Registers
001Ch-001Fh
0018h-001Bh
0000h-0003h
0014h-0017h
0100h-0103h
030Ch-030Fh
0308h-030Bh
0338h-033Bh
0200h-0203h
0204h-0207h
0300h-0303h
0334h-0337h
ADDRESS
ADDRESS
SU.MMCCTRL
SU.TxBytesOkCtr
SU.MACMIIA
SU.MACMIID
SU.MACFCR
SU.RxFrmOkCtr
SU.TxBdFrmCtr
SU.MACCR
SU.TxFrmUndr
REGISTER
SU.TxBytesCtr
SU.RxFrmCtr
SU.TxFrmCtr
REGISTER
MAC Control Register. This register is used for programming full
duplex, half duplex, promiscuous mode, and back-off limit for half
duplex. The transmit and receive enable bits must be set for the MAC
to operate.
MAC MII Management (MDIO) Address Register. The address for
PHY access through the MDIO interface.
MAC MII (MDIO) Data Register. Data to be written to (or read from)
the PHY through MDIO interface.
MAC Flow Control Register
MAC MMC Control Register. Bit 0 for resetting the status counters.
All frames received counter.
Number of received frames that are good.
Number of frames transmitted.
Number of bytes transmitted.
Number of bytes transmitted with good frames.
Transmit FIFO underflow counter.
Transmit number of frames aborted.
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DESCRIPTION
DESCRIPTION

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