DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 311

IC ETH TXRX T1/E1/J1 256-BGA

DS33R11+

Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS33R11+

Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Figure 12-26. Transmit-Side Boundary Timing (Elastic Store Disabled)
Figure 12-27. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store
Enabled)
TSYSCLK
TCHBLK
TCHCLK
TSSYNC
TSERI
TCHBLK
TCHCLK
TSYNC
TSYNC
TCLKT
NOTE 1: TSYNC IS IN THE OUTPUT MODE (TR.IOCR1.1 = 1).
NOTE 2: TSYNC IS IN THE INPUT MODE (TR.IOCR1.1 = 0).
NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
NOTE 5: THE SIGNALING DATA AT TSIG DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT FORMATTER
WITH THE CAS MF ALIGNMENT NIBBLE (0000).
NOTE 6: SHOWN IS A TNAF FRAME BOUNDARY.
NOTE 1: THE F-BIT POSITION IN THE TSERI DATA IS IGNORED.
NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
TSERI
TSIG
1
2
1
2
3
LSB
D
CHANNEL 23
Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8
CHANNEL 1
LSB MSB
CHANNEL 1
311 of 344
CHANNEL 24
MSB
LSB
CHANNEL 2
CHANNEL 2
A
F MSB
B
C
LSB MSB
CHANNEL 1
D

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