DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 29

• Manufacturer Part Number: DS33R11+
• Description: IC ETH TXRX T1/E1/J1 256-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R11+

• Protocol: T1/E1/J1
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

SBA[0]
SBA[1]
NAME
SDCS
MDIO
SCAS
SRAS
MDC
SWE
W10
C19
C20
V10
Y11
V11
PIN
W7
W9
TYPE
IO
O
O
O
O
O
O
PHY MANAGEMENT BUS
Management Data Clock (MII): Clocks management data between
the PHY and DS33R11. The clock is derived from theSYSCLKI,
with a maximum frequency is 1.67MHz. The user must leave this
pin unconnected in the DCE Mode.
MII Management data IO (MII): Data path for control information
between the PHY and DS33R11. When not used, pull to logic high
externally through a 10kΩ resistor. The MDC and MDIO pins are
used to write or read up to 32 Control and Status Registers in 32
PHY Controllers. This port can also be used to initiate Auto-
Negotiation for the PHY. The user must leave this pin unconnected
in the DCE Mode.
SDRAM Column Address Strobe: Active-low output, used to latch
the column address on the rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode Register Write.
SDRAM Row Address Strobe: Active-low output, used to latch
the row address on rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode Register Write.
SDRAM Chip Select: Active-low output enables SDRAM access.
SDRAM Write Enable: This active-low output enables write
operation and auto precharge.
SDRAM Bank Select: These 2 bits select 1 of 4 banks for the
read/write/precharge operations.
Note: All SDRAM operations are controlled entirely by the
DS33R11. No user programming for SDRAM buffering is required.
SDRAM INTERFACE
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FUNCTION