DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 258

IC ETH TXRX T1/E1/J1 256-BGA

DS33R11+

Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS33R11+

Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Transmit-Clock Edge Select (TCES). Selects which TDCLKI edge to sample TPOSI and TNEGI.
Bit 5: Receive-Clock Edge Select (RCES). Selects which RDCLKO edge to update RPOSO and RNEGO.
Bits 3 – 4: Monitor Mode (MM0 to MM1)
Bit 2: Receive Synchronization G.703 Clock Enable (RSCLKE)
Bit 1: Transmit Synchronization G.703 Clock Enable (TSCLKE)
Bit 0: Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (customer disconnect
indication signal) at TTIP and TRING. The transmission of this data pattern is always timed off of TCLKT.
MM1
0
0
1
1
0 = sample TPOSI and TNEGI on falling edge of TDCLKI
1 = sample TPOSI and TNEGI on rising edge of TDCLKI
0 = update RPOSO and RNEGO on rising edge of RDCLKO
1 = update RPOSO and RNEGO on falling edge of RDCLKO
0 = disable 1.544MHz (T1)/2.048MHz (E1) synchronization receive mode
1 = enable 1.544MHz (T1)/2.048MHz (E1) synchronization receive mode
0 = disable 1.544MHz (T1)/2.048MHz (E1) transmit synchronization clock
1 = enable 1.544MHz (T1)/2.048MHz (E1) transmit synchronization clock
0 = disabled
1 = enabled
MM0
0
1
0
1
7
0
Normal operation (no boost)
20
26
32
Internal Linear Gain Boost
TR.LIC3
Line Interface Control 3
7Ah
TCES
6
0
(dB)
RCES
5
0
258 of 344
MM1
0
4
MM0
3
0
RSCLKE
2
0
TSCLKE
1
0
TAOZ
0
0

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