DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 201

• Manufacturer Part Number: DS33R11+
• Description: IC ETH TXRX T1/E1/J1 256-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R11+

• Protocol: T1/E1/J1
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

11.7 T1/E1/J1 Transceiver Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 2 – 3: Test Mode Bits (TEST0, TEST1) Test modes are used to force the output pins of the transceiver into
known states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to
isolate devices from shared buses.
Bit 1: Transceiver Operating Mode (T1/E1) Used to select the operating mode of the framer/formatter (digital)
portion of the Transceiver. The operating mode of the LIU must also be programmed.
Bit 0: Software-Issued Reset (SFTRST) A 0-to-1 transition causes the register space in the T1/E1/J1 transceiver
to be cleared. A reset clears all configuration and status registers. The bit automatically clears itself when the reset
has completed.
TEST1
0
0
1
1
0 = T1 operation
1 = E1 operation
TEST0
—
0
1
0
1
7
0
Operate normally
Force all output pins into tri-state (including all I/O pins and parallel port pins)
Force all output pins low (including all I/O pins except parallel port pins)
Force all output pins high (including all I/O pins except parallel port pins)
TR.MSTRREG
Master Mode Register
00h
—
6
0
—
5
0
Effect On Output Pins
201 of 344
—
0
4
TEST1
3
0
TEST0
2
0
T1/E1
1
0
SFTRST
0
0