DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 225
DS33R11+
Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS33R11.pdf
(344 pages)
Specifications of DS33R11+
Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
- Current page: 225 of 344
- Download datasheet (12Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Transmit Message-End Event (TMEND). Set when the transmit HDLC controller has finished sending a
message. This is a latched bit and is cleared when read.
Bit 5: Receive Packet-End Event (RPE). Set when the HDLC controller detects either the finish of a valid
message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC
checking error, or an overrun condition, or an abort has been seen. This is a latched bit and is cleared when read.
Bit 4: Receive Packet-Start Event (RPS). Set when the HDLC controller detects an opening byte. This is a
latched bit and is cleared when read.
Bit 3: Receive FIFO Above High-Watermark Condition (RHWM). Set when the receive 128-byte FIFO fills
beyond the high watermark as defined by the receive high-watermark register (TR.RHWMR).
Bit 2: Receive FIFO Not Empty Condition (RNE). Set when the receive 128-byte FIFO has at least 1 byte
available for a read.
Bit 1: Transmit FIFO Below Low-Watermark Condition (TLWM). Set when the transmit 128-byte FIFO empties
beyond the low watermark as defined by the transmit low-watermark register (TR.TLWMR).
Bit 0: Transmit FIFO Not Full Condition (TNF). Set when the transmit 128-byte FIFO has at least 1 byte
available.
—
7
0
TR.SR6, TR.SR7
HDLC #1 Status Register 6
HDLC #2 Status Register 7
20h, 22h
TMEND
6
0
RPE
5
0
225 of 344
RPS
0
4
RHWM
3
0
RNE
2
0
TLWM
1
0
TNF
0
0
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