DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 303

IC ETH TXRX T1/E1/J1 256-BGA

DS33R11+

Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS33R11+

Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
RMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of the 50 MHz REF_CLK. The
data is only valid if CRS_DV is high. The external PHY asynchronously drives CRS_DV low during carrier loss.
Figure 12-9. RMII Receive Interface Functional Timing
12.3
Figure 12-10. Receive-Side D4 Timing
Figure 12-11. Receive-Side ESF Timing
CRS_DV
REFCLK
RXD[1:0]
RFSYNC
RSYNC
RSYNC
RSYNC
FRAME#
FRAME#
RFSYNC
RSYNC
RSYNC
RSYNC
Transceiver T1 Mode Functional Timing
P
3
1
2
NOTE 1: RSYNC IN THE FRAME MODE (TR.IOCR1.5 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TR.IOCR1.6 = 0).
NOTE 2: RSYNC IN THE FRAME MODE (TR.IOCR1.5 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TR.IOCR1.6 = 1).
NOTE 3: RSYNC IN THE MULTIFRAME MODE (TR.IOCR1.5 = 1).
1
2
3
NOTE 1: RSYNC IN FRAME MODE (TR.IOCR1.4 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TR.IOCR1.6 = 0).
NOTE 2: RSYNC IN FRAME MODE (TR.IOCR1.4 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TR.IOCR1.6 = 1).
NOTE 3: RSYNC IN MULTIFRAME MODE (TR.IOCR1.4 = 1).
R
1
1
E
2
A
2
3
M
4
3
5
B
6
4
L
7
5
8
E
9 10 11 12
6
7
303 of 344
8
13 14 15 16 17 18 19 20 21 22 23 24 1
9
10
11
12
1
2
3
F
2
4
C
3
5
4
S
5

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