IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 44
IDT82V2108PX8
Manufacturer Part Number
IDT82V2108PX8
Description
IC FRAMER T1/J1/E1 8CH 128-PQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108PX8
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
82V2108PX8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V2108PX8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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IDT82V2108
Functional Description
RSCFS
RSDn
RSCCK
RSFSn
RSSIGn
Note:
* It is a special case when the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-010H) is equal to FE (b3, E1-010H). The signal on the RSDn,
RSSIGn and RSFSn are updated on the first active edge of RSCCK.
RSCFS
RSDn
RSCCK
RSSIGn
RSFSn
Figure 13. E1 Receive Clock Slave External Signaling Mode - Functional Timing Example 1
Figure 14. E1 Receive Clock Slave External Signaling Mode - Functional Timing Example 2
The DE (b4, E1-010H) is logic 1 and the FE (b3, E1-010H) is logic 1. * The timeslot offset and the bit offset enable are both 0:
X
1
1
X
X
2
The CMS (b2, E1-010H) is logic 0, i.e., the bankplane rate is 2.048Mbit/s. The DE (b4, E1-010H) is logic
2
X
X
3
1 and the FE (b3, E1-010H) is logic 0. The timeslot offset and the bit offset enable are both 0:
3
X
X
4
TS31
4
X
The CMS (b2, E1-010H) is logic 1, i.e., the bankplane rate is 4.096Mbit/s.
A
5
TS31
5
A
B
6
6
B
C
7
(The 'X' represents the filled bits and has no meaning. The 'P' represents the Parity bit..)
7
C
D
8
D
8
1
P
(The 'X' represent the filled bits and has no meaning. The 'P' represents the Parity bit..)
1
P
2
X
2
X
X
3
34
X
3
X
4
TS0
X
4
X
5
TS0
5
X
X
6
6
X
X
7
7
X
X
8
8
X
1
X
1
X
2
X
2
X
3
X
TS1
T1 / E1 / J1 OCTAL FRAMER
3
X
X
4
TS1
4
X
A
5
5
A
B
6
6
B
March 5, 2009
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