IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 130

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
transmit-receive integrity and system backplane integrity.
- Example For Testing T1/J1 Line Transmit-Receive Integrity
T1/J1 offline. Following procedure should be done.
insert/extract PRGD test data;
nels;
Table 59 should be set.
shows the process to initialize the TPLC. Table 59 shows the process to
initialize the RPLC.
Table 58: Initialization of TPLC
Operation
Table 57: Setting of PRGD
Register
00FH
06BH
08AH
0B0H
0D0H
060H
062H
063H
068H
The PRBS generator/detector block can be used to test T1/J1 line
Suppose to monitor the errors in Framer 2 without taking the entire
- Select Framer 2 to be tested by the PRGD block;
- Configure the PRGD register;
- Chose a desired set of channels (for example CH2, CH4, CH5) for
- Set the far end of the line to loop back at least the selected chan-
- Monitor the T1/J1 line transmit-receive integrity.
To realize the above function, the configuration in Table 57 to
Table 57 is the configuration for PRGD and loopback. Table 58
Register
Value
FFH
FFH
20H
82H
18H
02H
04H
01H
01H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
Select Framer 2 to be tested by the PRGD block. The
PRGD pattern is inserted in the TPLC and detected in
the RPLC.
Set Pattern Detector registers as error counter regis-
ters. Enable automatic resynchronization.
Set the pattern length.
Set the feedback tap position.
Set the Pattern Insertion registers.
Load the data in the Pattern Insertion registers to gen-
erate the pattern.
Set diagnostic digital loopback mode.
Enable the TPLC indirect registers to be accessible.
Enable the RPLC indirect registers to be
Description
Value
00H
01H
00H
02H
00H
03H
00H
04H
00H
05H
00H
accessible.
120
Table 58: Initialization of TPLC (Continued)
Register
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
0B3H
0B2H
T1 / E1 / J1 OCTAL FRAMER
Value
0CH
0DH
06H
00H
07H
00H
08H
00H
09H
00H
0AH
00H
0BH
00H
00H
00H
0EH
00H
0FH
00H
10H
00H
00H
12H
00H
13H
00H
14H
00H
15H
00H
16H
00H
17H
00H
18H
00H
31H
00H
32H
00H
33H
00H
34H
00H
35H
11H
March 5, 2009