IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 26

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

Table 2: Interrupt Sources in the E1 Frame Processor
IDT82V2108
declared with a logic ‘1’ in the AIS (b2, E1-037H). However, in unframed
mode, the detection of AIS alarm is disabled.
3.2.1.2.3
to Sa8[1:4] in the CRC Sub Multi-Frame), the International bit (Si), the
National bit (Sa), the Remote Alarm Indication bit (A), the Extra bits (X)
and the Remote Signaling Multi-Frame Alarm Indication bit (Y).
- National Bit Codeword
(Sa4[1:4] to Sa8[1:4] in the CRC Sub Multi-Frame) to the SaX[1:4]
(b3~0, E1-03DH). Here the ‘X’ is selected from 4 to 8 by the SaSEL[2:0]
(b7~5, E1-03BH). The SaX[1:4] (b3~0, E1-03DH) are debounced. They
are updated only when two consecutive codewords are the same.
- International Bit
038H). The Si[1:0] (b7~6, E1-038H) are updated on the boundary of the
associated FAS/NFAS frame and are not updated when out of frame is
reported.
038H). The Sa[4:8] (b4~0, E1-038H) are updated on the boundary of the
associated NFAS frame and are not updated when out of frame is
reported.
- Remote Alarm Indication Bit
Functional Description
No.
1 The received Basic Frame alignment signal does not meet its pattern once Basic
2 The received CRC Multi-Frame alignment signal does not meet its pattern once
3 The received Signaling Multi-Frame alignment signal does not meet its pattern
4 The received data stream is out of Basic Frame synchronization when any of the
5 The received data stream is out of CRC Multi-Frame synchronization when any of
6 The received data stream is out of Signaling Multi-Frame synchronization when
When the above status has lasted for 100 ms, AIS alarm is
The Frame Processor extracts the National Bit codeword (Sa4[1:4]
- National Bit
The Frame Processor extracts one of the National Bit codewords
Frame synchronization is achieved.
CRC Multi-Frame synchronization is achieved.
once Signaling Multi-Frame synchronization is achieved.
following conditions is met:
1) The Basic Frame has not been synchronized.
2) The received data stream meets the out of Basic Frame synchronization criteria
set in the BIT2C (b6, E1-031H).
3) There are excessive CRC errors in the received data stream.
the following conditions is met:
1) The CRC Multi-Frame has not been synchronized.
2) There are excessive CRC errors in the received data stream.
any of the following conditions is met:
1) The received data stream is out of Basic Frame synchronization.
1) The received data stream meets the out of Signaling Multi-Frame synchroniza-
tion criteria set in the SMFASC (b5, E1-031H) and the TS16C (b4, E1-031H).
The International bits (Si) are extracted to the Si[1:0] (b7~6, E1-
The National bits (Sa) are extracted to the Sa[4:8] (b4~0, E1-
Bit Extraction
Sources
16
038H). The A (b5, E1-038H) is updated on the boundary of the associ-
ated NFAS frame.
- Extra Bit
03AH). The X[0:2] (b5 & b3~2, E1-03AH) are updated on the beginning
of the Frame1 (next NFAS frame).
- Remote Signaling Multi-Frame Alarm Indication Bit
extracted to the Y (b4, E1-03AH). The Y (b4, E1-03AH) is updated on
the beginning of the Frame1 (next NFAS frame).
3.2.1.2.4
detected with the indication in the V52LINKV (b0, E1-036H).
3.2.1.3
Table 2. When there are conditions meeting the interrupt sources, the
corresponding Status bit will be asserted high. When there is a transition
(‘1’ to ‘0’ or ‘0’ to ‘1’) on the Status bit, the corresponding Status Interrupt
Indication bit will be set to logic 1 (If the Status bit does not exist, the
source will cause its Status Interrupt Indication bit to logic 1 directly) and
the Status Interrupt Indication bit will be cleared when it is read. A logic 1
in the Status Interrupt Indication bit means an interrupt occurred. The
interrupt will be reported by the INT pin if its Status Interrupt Enable bit is
logic 1.
OOFV (b6, E1-
OOCMFV (b4,
OOSMFV (b5,
The Remote Signaling Multi-Frame Alarm Indication bit (Y) is
The V5.2 link ID signal, i.e. 2 out of 3 Sa7 bits being logic 0, is
24 kinds of interrupts are derived from this block as shown in
The Remote Alarm Indication bit (A) is extracted to the A (b5, E1-
The Extra bits (X) are extracted to the X[0:2] (b5 & b3~2, E1-
Status Bit
E1-036H)
E1-036H)
036H)
-
-
-
Interrupt Sources
V5.2 Link
Interrupt Indication Bit
OOCMFI (b4, E1-034H)
OOSMFI (b5, E1-034H)
CMFERI (b0, E1-034H)
SMFERI (b1, E1-034H)
OOFI (b6, E1-034H)
FERI (b2, E1-034H)
T1 / E1 / J1 OCTAL FRAMER
OOCMFE (b4, E1-032H)
CMFERE (b0, E1-032H)
OOSMFE (b5, E1-032H)
SMFERE (b1, E1-032H)
OOFE (b6, E1-032H)
Interrupt Enable Bit
FERE (b2, E1-032H)
March 5, 2009