IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 19

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
Pin Description
LTCK[1]
LTCK[2]
LTCK[3]
LTCK[4]
LTCK[5]
LTCK[6]
LTCK[7]
LTCK[8]
Name
A[10]
XCK
RST
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
ALE
INT
WR
CS
RD
Output /
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
PQFP PBGA
117
10
12
14
16
23
25
27
29
39
65
40
54
55
56
57
58
59
60
61
62
63
64
41
42
43
44
45
46
47
48
67
66
53
Pin No.
M11 CS: Chip Select (Active Low)
M10
L10
K10 WR: Write Strobe (Active Low)
L11 RD: Read Strobe (Active Low)
M2
M8
M9
M3
M4
M5
C1
D1
F3
E2
H2
H3
H4
B6
K7
K8
K9
K5
K6
J1
J5
L8
L9
J8
J9
L4
J6
L5
L7
LTCKn: Line Transmit Clock for Framer 1 ~ 8
It is a nominal E1 (2.048MHz) or T1/J1 (1.544MHz) clock. LTCK can be derived from TSCCKA, TSCCKB, LRCK or
XCK. On the active edge of LTCKn, the corresponding LTDn is updated.
XCK: Crystal Clock
The clock frequency equals 49.152MHz ± 50 ppm 50% duty cycle for E1 and 37.056MHz ± 32 ppm 50% duty cycle
for T1/J1.
RST: Reset (Active Low)
A low signal for at least 100 ns on this pin will reset the device anytime. RST is a Schmitt-trigger input with weak
pull-up.
This pin must be asserted low to enable the microprocessor interface. The signal must be asserted high at least
once after power up to clear the internal test modes. A transition from high to low must occur on this pin for each
Read/Write operation and can not return to high until the operation is over.
INT: Open-Drain Interrupt Signal (Active Low)
This pin will keep low until all the active unmasked interrupt are acknowledged at their sources.
A[10:0]: Address Bus
The signals on these pins select the register for the microprocessor to access.
D[7:0]: Bi-directional Data Bus
Signals on these pins are the data for Read/Write operation.
A low signal on this pin enables a read operation on the selected register.
A low signal on this pin enables a write operation on the selected register.
ALE: Address Latch Enable
In non-multiplexed address/data bus, the ALE is connected to High.
It is internally pulled-up.
Microprocessor Interface
JTAG (per IEEE 1149.1)
9
Description
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009