IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 110

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
example is shown in Table 43.
Table 43: Example for Using HDLC Receiver
4.1.3.2
must be set to ‘1’ to enable the HDLC data link position for transmit path.
one of the three HDLC Transmit data links must be selected in the
THDLCSEL[1:0] (b5~4, E1-00AH). Then the HDLC data link can be con-
figured to insert to even and/or odd frames, to any time slot, and to any
bit. The following examples show how to select the HDLC Transmit data
link positions:
#1:
Transmit #1:
Transmit #3:
Operation
Then read the data status in register 04AH. Until a complete packet is
received, read the data from register 04BH.
Register
00AH
02AH
02BH
04CH
04DH
048H
049H
To summarize the procedure of using HDLC Receive, a complete
Before using the HDLC Transmit, the TXCISEL (b3, E1-00AH)
Since three HDLC Transmit data links are integrated in one framer,
a. Insert the HDLC data link to all bits of TS16 in HDLC Transmit
- set the TXCISEL (b3, E1-00AH) to ‘1’;
- set the THDLCSEL [1:0] (b5~4, E1-00AH) to ‘00’;
- set the DL1_EVEN (b7, E1-028H) to ‘0’;
- set the DL1_ODD (b6, E1-028H) to ‘0’;
- set the TS16_EN (b5, E1-028H) to ‘1’.
b. Insert the HDLC data link to the Sa4-Sa8 National bits in HDLC
- set the TXCISEL (b3, E1-00AH) to ‘1’;
- set the THDLCSEL [1:0] (b5~4, E1-00AH) to ‘00’;
- set the DL1_EVEN (b7, E1-028H) to ‘0’;
- set the DL1_ODD (b6, E1-028H) to ‘1’;
- set the TS16_EN (b5, E1-028H) to ‘0’;
- set the DL1_TS[4:0] (b4~0, E1-028H) to ‘00000’;
- set the DL1_BIT[7:0] (b7~0, E1-029H) to ‘00011111’.
c. Insert the HDLC data link to all bits of TS20 of all frames in HDLC
- set the TXCISEL (b3, E1-00AH) to ‘1’;
- set the THDLCSEL [1:0] (b5~4, E1-00AH) to ‘10’;
- set the DL3_EVEN (b7, E1-02CH) to ‘1’;
- set the DL3_ODD (b6, E1-02CH) to ‘1’;
- set the DL3_TS [4:0] (b4~0, E1-02CH) to ‘10100’;
- set the DL3_BIT [7:0] (b7~0, E1-02DH) to ‘11111111’.
Value
C4H
FFH
0DH
8FH
FFH
50H
13H
Using HDLC Transmitter
RHDLC #2 is selected. The HDLC Receive is accessible
to the CPU interface.
The TS4 of even frames and odd frames is selected.
All 8 bits are selected.
The function of the RHDLC #2 is enabled. Set the
address match mode.
Set the INTE to ‘1’. When the number of bytes in the
RHDLC FIFO exceeds 15, an interrupt is generated.
The primary address is set to ‘13H’.
The secondary address is set to ‘FFH’.
Description
100
HDLC Transmit should be enabled by setting the EN (b0, E1-050H) to
logic 1. The FIFOCLR (b6, E1-050H) should be set and then cleared to
initialize the THDLC FIFO.
Sequences (FCS) generation is desired. Set the FULLE (b3, E1-053H),
OVRE (b2, E1-053H), UDRE (b1, E1-053H) and LFILLE (b0, E1-053H)
to logic 1 if interrupt driven mode is used. Set THDLC Upper Transmit
Threshold and THDLC Lower Transmit Threshold registers to the
desired values. If a complete packet has been written into THDLC FIFO,
the EOM (b3, E1-050H) should be set.
mitted in a polled or interrupt driven mode.
- Interrupt Driven Mode
HDLC data if the end of a packet was written or if the THDLC FIFO fill
level reaches the Upper Transmit Threshold. The writing procedure is
shown in Figure 74.
E1-053H) and LFILLE (b0, E1-053H) are set to logic 1, the source of the
interrupt should be identified firstly by reading the Interrupt ID register
and Interrupt Source registers if the INT pin is asserted. If the source of
the interrupt is HDLC Transmit, the Interrupt Service procedure will be
carried out as shown in Figure 75.
Figure 74. Writing Data to E1 Mode THDLC FIFO
After setting the HDLC data link position properly, the selected
Set the CRC (b1, E1-050H) to logic 1 if the Frame Check
After setting these registers properly, the HDLC data can be trans-
Writing HDLC data to THDLC FIFO, the THDLC will transmit the
When the FULLE (b3, E1-053H), OVRE (b2, E1-053H), UDRE (b1,
Data is available
Write data into
End of packet
THDLC FIFO
THDLC Initial
Set EOM
Y
Y
T1 / E1 / J1 OCTAL FRAMER
N
N
March 5, 2009