IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 123

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IDT82V2108PX8

Manufacturer Part Number
IDT82V2108PX8
Description
IC FRAMER T1/J1/E1 8CH 128-PQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT82V2108PX8

Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
82V2108PX8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT82V2108PX8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT82V2108
Table 53: Various Operation Modes in Transmit Path for Reference (Continued)
Operation
Note:
1. In the ‘Register’ column, except for the Receive/Transmit Multiplexed mode, the register position of Framer 1 is listed to represent the set of the registers of eight framers. The other reg-
isters positions are tabulated in the ‘Register Map’. However, in the Receive/Transmit Multiplexed mode, the registers positions of the eight framers are all listed.
2. The ‘Description’ illustrates the fundamental function of the operation mode. The others can be configured as desired.
Transmit Multi-
plexed Mode
(Continued)
Mode
Register
01AH
09AH
19AH
21AH
29AH
31AH
39AH
01BH
09BH
19BH
21BH
29BH
31BH
39BH
007H
087H
107H
187H
207H
287H
307H
387H
019H
099H
119H
199H
219H
299H
319H
399H
11AH
11BH
1
Value (from Bit7 to Bit0)
11000000
11000000
11000000
11000000
11000000
11000000
11000000
11000000
00010000
00010000
00010000
00010000
00010000
00010000
00010000
00010000
00011101
00011101
00011101
00011101
00011101
00011101
00011101
00011101
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
TSCCKA is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit
Clock (LTCK).
Set the Reference Clock Divisor(N1) to ‘255’.
Set the Output Clock Divisor(N2) to ‘192’.
The FIFO is set to self-center its read pointer.
113
Description
2
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009

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