IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 242

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
T1 / J1 ALMD Alarm Detection Status (02FH, 0AFH, 12FH, 1AFH, 22FH, 2AFH, 32FH, 3AFH)
REDD:
YELD:
period.
nal is present during the latest 40 ms period, when the AVC (b1, T1/J1-02AH) is ‘1’, the Yellow signal is present during the latest 20 ms period.
the Yellow signal is present.
period, the Yellow signal is present.
When the AVC (b1, T1/J1-02AH) is logic 0, the Yellow signal is acknowledged if the pattern is matched in 8 out of 10 successive DL. When the AVC
(b1, T1/J1-02AH) is logic 1, the Yellow signal is acknowledged if the pattern is matched in 4 out of 5 successive DL.
AISD:
times in the same period.
T1 / J1 TPLC Configuration (030H, 0B0H, 130H, 1B0H, 230H, 2B0H, 330H, 3B0H)
PCCE:
Programming Information
Bit Name
Bit Name
Default
Bit No.
Default
Bit No.
Type
= 0: No out of SF/ESF synchronization event has occurred in the latest 40 ms period.
= 1: One or more out of SF/ESF synchronization events have occurred in the latest 40 ms period.
= 0: In SF format, the Yellow signal is absent during the latest 40 ms period; in ESF format, the Yellow signal is absent during the latest 4 ms
= 1: In SF format, the Yellow signal is present during the latest 40 ms period; in ESF format, when the AVC (b1, T1/J1-02AH) is ‘0’, the Yellow sig-
The Yellow signal is acknowledged differently in each format:
- In T1 SF format: The Yellow signal occupies the 2nd bit of each channel. When the bit is logic 1 for 16 or fewer times during the 40 ms period,
- In J1 SF format: The Yellow signal occupies the F-bit of the 12th frame. However, when the bit is logic 0 for 2 or fewer times during the 40 ms
- In T1/J1 ESF format: The Yellow signal occupies the DL of the F-bit (refer to Table-4). The pattern is ëFF00í in T1 mode and ‘FFFF’ in J1 mode.
= 0: AIS signal is absent during the latest 60 ms period.
= 1: AIS signal is present during the latest 60 ms period.
The AIS signal is acknowledged when the received data is out of SF/ESF synchronization for 60 ms and the received logic 0 is less than 127
Type
= 0: The per-channel functions in TPLC are disabled.
= 1: The per-channel functions in TPLC are enabled.
7
7
6
6
Reserved
5
5
Reserved
4
4
232
3
3
REDD
R
2
X
2
T1 / E1 / J1 OCTAL FRAMER
YELD
R
X
1
1
March 5, 2009
PCCE
AISD
R/W
0
0
R
X
0