IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 184

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
E1 FRMG Configuration (040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H)
FRESH:
SIGEN, DLEN:
GENCRC:
the INDIS (b1, E1-040H) is enabled (logic 0), or, if the INDIS (b1, E1-040H) is not enabled, the International bits are taken directly from TSDn/MTSD.
Multi-Frame alignment pattern and calculated CRC-4 bits. The CRC bits calculated during the transmission of the SMFn are transmitted in the follow-
ing SMF (SMF n+1). If the FEBEDIS (b2, E1-040H) is enabled (logic 0), the FEBE indication is inserted in the E1 and E2 bit positions. This setting is
valid when the FDIS (b3, E1-040H) and the INDIS (b1, E1-040H) are logic 0.
FDIS:
040H), FEBEDIS (b2, E1-040H) and INDIS (b1, E1-040H) are ignored.
FEBEDIS:
INDIS:
selects this inserted position.
XDIS:
Programming Information
Bit Name
Default
SIGEN, DLEN
Bit No.
Type
= 0: Normal operation.
= 1: Initiate the FIFO in the Frame Generator block.
After initialization of the backplane interface, the user should write ‘1’ into this bit and then clear it.
These two bits select the signaling sources for TS16. They are valid when the AIS (b0, E1-041H) is logic 0:
= 0: CRC Multi-Frame generation is disabled. Then the International bits are replaced with the value contained in the Si[1:0] (b7~6, E1-042H) if
= 1: CRC Multi-Frame generation is enabled. When CRC Multi-Frame is generated, the International bits on the TSDn pin are replaced with CRC
= 0: Replace the data on TS0 of FAS on the TSDn/MTSD pin with Basic Frame alignment sequence (FAS).
= 1: Keep the data on the TSDn/MTSD pin to pass through the Frame Generation transparently. The values in the control bits GENCRC (b4, E1-
Valid when the FDIS (b3, E1-040H) and the INDIS (b1, E1-040H) are logic 0 and the GENCRC (b4, E1-040H) is logic 1.
= 0: The International bits of frame 13 & 15 are for FEBE indication.
= 1: FEBE indication is disabled.
= 0: Enabled to replace the International bit.
= 1: Disable to replace the International bit. The value of the international bit is directly taken from TSDn/MTSD or from the THDLC if the THDLC
Valid when the FDIS (b3, E1-040H) is logic 0, and the SIGEN (b6, E1-040H) and the DLEN (b5, E1-040H) are logic 1.
= 0: Replace the extra bits with the setting in the X[2:0].
0 0
0 1
1 0
1 1
FRESH
R/W
Signaling insertion disable or CCS enable. TS16 data is taken directly from the input TSDn TS16 or from the THDLC if the THDLC selects this
inserted position. The XDIS (b0, E1-040H) must also be set to logic 1 to disable the insertion of the extra bits in TS16 of frame 0.
Reserved
Reserved
CAS enable. TS16 data is taken from either TSSIGn stream or from the TPLC Signaling/PCM Control byte as selected on a per-time slot basis
via the SIGSRC (b4, E1-TPLC-indirect registers - 61~7FH). However, the TS16 of Frame0 of Signaling Multi-Frame is overwritten by
‘0000X[0]YX[1]X[2]’.
7
0
SIGEN
R/W
6
1
DLEN
R/W
5
1
GENCRC
R/W
4
0
174
Signaling Source
FDIS
R/W
3
0
FEBEDIS
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
INDIS
R/W
1
0
March 5, 2009
XDIS
R/W
0
0