IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 118

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
- Transmit Multiplexed Mode (System Backplane Rate: 8.192 Mbit/s)
CKA is equal to 2.048 M. The N1 (b7~0, E1-025H) and N2 (b7~0, E1-
026H) are set to their default value (2FH).
- Transmit Multiplexed Mode (System Backplane Rate: 16.384 Mbit/s)
ence clock. TSCCKA is equal to 2.048 M or 16.384 M. The N1 (b7~0,
E1-025H) and N2 (b7~0, E1-026H) are set to their default value (2FH).
Table 50: Default Setting in Receive Path in T1/J1 Mode
Table 51: Default Setting in Transmit Path in T1/J1 Mode
Operation
Line Interface
Frame Processor
HDLC Receiver #1, #2
Receive System Interface
Receive Payload Control
PRGD
PRGD
Transmit System Interface
Transmit Payload Control
Frame Generator
HDLC Transmitter #1, #2
Bit-Oriented Message Transmitter
Inband Loop-back Code Generator
Line Interface
TSCCKA is selected as the TJAT DPLL input reference clock. TSC-
The smoothed clock output from the TJAT is selected as LTCK.
TSCCKA or TSCCKA/8 is selected as the TJAT DPLL input refer-
The smoothed clock output from the TJAT is selected as LTCK.
Function Block
Function Block
- LRDn inputs Non-Return to Zero (NRZ) data and is sampled on the rising edge of LRCKn.
- The RJAT Clock Divisors (N1, N2) are set to ‘2F’.
- Super Frame (SF) format is enabled.
- RHDLCs are disabled.
- In the Receive Clock Slave External Signaling Mode.
- The data on the RSDn, RSSIGn pins are updated on the falling edge of RSCCK.
- RSCFS indicates each F-bit.
- The data on the RSDn, RSSIGn, RSFSn pins are held in high-impedance state.
- The RPLC is disabled.
- The PRGD is configured to monitor the extracted data patterns in Frame 1.
- The PRGD is configured to insert test patterns to Frame 1.
- In the Transmit Clock Slave External Signaling Mode.
- The data on the TSDn and TSSIGn pins are sampled on the rising edge of TSCCKB.
- The TPLC is disabled.
- Super Frame (SF) format is enabled.
- The THDLCs are disabled.
- The BOMT is disabled.
- The Inband Loop-back Code Generator is disabled.
- LTDn outputs Non-Return to Zero (NRZ) data and is updated on the falling edge of LTCKn.
- TJAT Clock Divisors (N1, N2) are set to ‘2F’.
- Digital jitter attenuation is enabled. The PLL is synchronized to the TSCCKB clock. The smoothed clock output from
the PLL is selected as LTCKn.
108
4.2
4.2.1
values.
(b0, E1-00AH / b0, T1/J1-00DH) in its framer is set. The device can also
be reset anytime when the RST pin is low for at least 100 ns.
ing settings:
is illustrated in Table 50.
path is illustrated in Table 51.
Default Setting Description
When the device is powered-up, all the registers are in their default
Any of the eight framers can be reset anytime when the RESET
After the hardware reset, the IDT82V2108 will default to the follow-
- Mode: the default operation mode of the device is T1 mode.
- Receive Path: the default setting of each block in the receive path
- Transmit Path: the default setting of each block in the transmit
Default Setting Description
T1/J1 MODE
DEFAULT SETTING
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009