IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 157
IDT82V2108PX8
Manufacturer Part Number
IDT82V2108PX8
Description
IC FRAMER T1/J1/E1 8CH 128-PQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108PX8
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
82V2108PX8
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V2108PX8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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IDT82V2108
E1 Transmit Backplane Configuration (018H, 098H, 118H, 198H, 218H, 298H, 318H, 398H)
TSCKSLV:
DE:
FE:
CMS:
RATE[1:0]:
plane bit rate, the multiplexed bus will be enabled for the chip. When the RATE[1:0] select the 8.192 Mbit/s, the TSCKSLV (b5, E1-018H) must be set
to ‘1’.
Programming Information
Bit Name
Default
Bit No.
Type
= 0: Transmit Clock Master mode is enabled.
= 1: Transmit Clock Slave mode or Transmit Multiplexed mode is enabled.
= 0: The data on the TSDn/MTSD and TSSIGn/MTSSIG pins is sampled on the falling edge of TSCCKB/MTSCCKB or LTCKn.
= 1: The data on the TSDn/MTSD and TSSIGn/MTSSIG pins is sampled on the rising edge of TSCCKB/MTSCCKB or LTCKn.
In Transmit Multiplexed mode, the DE of the eight framers should be set to the same value.
Valid in Transmit Clock Slave mode and Transmit Multiplexed mode.
= 0: The data on the TSCFS/MTSCFS pin is sampled on the falling edge of TSCCKB/MTSCCKB.
= 1: the data on the TSCFS/MTSCFS pin is sampled on the rising edge of TSCCKB/MTSCCKB.
In Transmit Multiplexed mode, the FE of the eight framers should be set to the same value.
= 0: The clock rate of TSCCKB/MTSCCKB is the same as that of the backplane.
= 1: The clock rate of TSCCKB/MTSCCKB is double that of the backplane.
The CMS of the eight framers should be set to the same value.
These bits determine the bit rate of the transmit data stream on the backplane. Note that if any of the eight framers selects the 8.192 Mbit/s back-
7
Reserved
6
RATE[1:0]
0 0
0 1
1 0
1 1
TSCKSLV
R/W
5
1
R/W
DE
4
1
147
8.192M bit/s (valid to eight frames)
Backplane Rate
2.048M bit/s
Reserved
Reserved
R/W
FE
3
1
CMS
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
RATE[1]
R/W
1
0
March 5, 2009
RATE[0]
R/W
0
0
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