COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 68

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

Revision 09-27-07
nIOCS16
D0-D15
A0-A2
*
**** t11 is measured from the latest active (valid) timing among nCS, A0-A2.
*****
Note 1:
**
Note 3:
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
nWR
nRD
nCS
T
T
T
T
t5
Note 2:
t1
t2
t3
t4
t6
t7
t8
t9
t10
t11
t12
Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
opr
ARB
ARB
ARB
t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
Cycle Time (nWR
Address Setup to nWR Active
Address Hold from nWR Inactive
nCS Setup to WR Active
nCS Hold from nWR Inactive
Valid Data Setup to nWR High
Data Hold from nWR High
nWR Low Width
nWR High Width
nRD
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Any cycle occurring after a write to Address Pointer Low Register requires a
next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5T
leading edge of the next nWR.
minimum of 4T
Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5T
leading edge of nWR.
opr
to nWR Low
if SLOW ARB = 1
Parameter
Note 3
opr
t10
t1
if SLOW ARB = 0
ARB
CASE 2: BUSTMG pin = LOW
from the trailing edge of nWR to the leading edge of the
t3
to Next
DATASHEET
t11
)
**
ARB
ARB
Page 68
VALID
from the trailing edge of nWR to the
from the trailing edge of nRD to the
t8
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
VALID DATA
VALID VALUE
4T
0*****
t6
min
10
65
30
20
30
ARB
0
0
0
0
*
40****
max
t7
t2
Note 2
t4
t5**
t9
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t12
t5
SMSC COM20022I
Datasheet