COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 50

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

6.6.3
Revision 09-27-07
message is not a BROADCAST, the COM20022I automatically sends a FREE BUFFER ENQUIRY to the
destination node in order to send the message. At this point, one of four possibilities may occur.
The first possibility is if a free buffer is available at the destination node, in which case it responds with an
ACKnowledgement. At this point, the COM20022I fetches the data from the Transmit Buffer and performs the
transmit sequence. If a successful transmit sequence is completed, the TMA bit and the TA bit are set to
logic "1". If the packet was not transmitted successfully, TMA will not be set. A successful transmission
occurs when the receiving node responds to the packet with an ACK. An unsuccessful transmission occurs
when the receiving node does not respond to the packet.
The second possibility is if the destination node responds to the Free Buffer Enquiry with a Negative
AcKnowledgement. A NAK occurs when the RI bit of the destination node is a logic "1". In this case, the
token is passed on from the transmitting node to the next node. The next time the transmitter receives the
token, it will again transmit a FREE BUFFER ENQUIRY. If a NAK is again received, the token is again
passed onto the next node. The Excessive NAK bit of the Diagnostic Status Register is used to prevent an
endless sending of FBE's and NAK's. If no limit of FBE-NAK sequences existed, the transmitting node would
continue issuing a Free Buffer Enquiry, even though it would continuously receive a NAK as a response. The
EXCNAK bit generates an interrupt (if enabled) in order to tell the microcontroller to disable the transmitter via
the "Disable Transmitter" command. This causes the transmission to be abandoned and the TA bit to be set
to a logic "1" when the node next receives the token, while the TMA bit remains at a logic "0". Please refer to
the Improved Diagnostics section for further detail on the EXCNAK bit.
The third possibility which may occur after a FREE BUFFER ENQUIRY is issued is if the destination node
does not respond at all. In this case, the TA bit is set to a logic "1", while the TMA bit remains at a logic "0".
The user should determine whether the node should try to reissue the transmit command.
The fourth possibility is if a non-traditional response is received (some pattern other than ACK or NAK, such
as noise). In this case, the token is not passed onto the next node, which causes the Lost Token Timer of the
next node to time out, thus generating a network reconfiguration.
The "Disable Transmitter" command may be used to cancel any pending transmit command when the
COM20022I next receives the token. Normally, in an active network, this command will set the TA status bit
to a logic "1" when the token is received. If the "Disable Transmitter" command does not cause the TA bit to
be set in the time it takes the token to make a round trip through the network, one of three situations exists.
Either the node is disconnected from the network, or there are no other nodes on the network, or the external
receive circuitry has failed. These situations can be determined by either using the improved diagnostic
features of the COM20022I or using another software timeout which is greater than the worst case time for a
round trip token pass, which occurs when all nodes transmit a maximum length message.
Receive Sequence
A receive sequence begins with the RI status bit becoming a logic "1", which indicates that a previous
reception has concluded. The microcontroller will be interrupted if the corresponding bit in the Interrupt Mask
Register is set to logic "1". Otherwise, the microcontroller must periodically check the Status Register. Once
the microcontroller is alerted to the fact that the previous reception has concluded, it may issue the "Enable
Receive to Page fnn" command, which resets the RI bit to logic "0" and selects a new page in the RAM
buffer. Again, the appropriate buffer size is specified in the "Define Configuration" command. Typically, the
page which just received the data packet will be read by the microcontroller at this point. Once the "Enable
Receive to Page fnn" command is issued, the microcontroller attends to other duties.
There is no way of knowing how long the new reception will take, since another node may transmit a packet
at any time. When another node does transmit a packet to this node, and if the "Define Configuration"
command has enabled the reception of long packets, the COM20022I interprets the packet as either a long
or short packet, depending on whether the content of the buffer location 2 is zero or non-zero. The format of
the buffer is shown in Figure 5.7. Address 0 contains the Source Identifier (SID), Address 1 contains the
Destination Identifier (DID), and Address 2 contains, for short packets, the value 256-N, where N represents
the message length, or for long packets, the value 0, indicating that it is indeed a long packet. In the latter
case, Address 3 contains the value 512-N, where N represents the message length. Note that on reception,
DATASHEET
Page 50
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
SMSC COM20022I
Datasheet