COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 61

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I
nIOCS16
AD0-AD2,
D3-D15
**
nCS
ALE
nDS
DIR
Note 1:
Note 2:
*
Note 2 is applied to an access to Data Register by DMA transfer.
T
T
T
T
Figure 8.3
t10
t11
t12
t13
t14
t15
t16
ARB
ARB
ARB
opr
t1
t2
t3
t4
t5
t6
t7
t8
t9
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
Any cycle occurring after a write to Address Pointer Low Register requires a
next nDS.
Write cycle for Address Pointer Low Register occurring after an access to
Data Register requires a minimum of 5T
the leading edge of the next nDS.
minimum of 4T
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High
Cycle Time (nDS
ALE High Width
ALE Low Width
nDS Low Width
nDS High Width
nIOCS16 Hold Delay from ALE Low
nIOCS16 Output Delay from ALE Low
DIR Setup to nDS Active
DIR Hold from nDS Inactive
Previous Value
opr
- Multiplexed Bus, 68XX-Like Control Signals Write Cycle
if SLOW ARB = 1
t11
t1
opr
VALID
t3
if SLOW ARB = 0
ARB
MUST BE: BUSTMG pin = HIGH
from the trailing edge of nDS to the leading edge of the
Parameter
t15
to Next
t2,
t4
t5
DATASHEET
t9
Invalid
t16
)**
Page 61
ARB
from the trailing edge of nDS to
t12
VALID DATA
t13
t6
4T
Valid Value
min
10
10
20
20
20
20
30
10
20
10
10
10
15
0
ARB
*
max
40
t7
t10
t14
Note 2
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t8**
t8
Revision 09-27-07