COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 23

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I
Read/Write
Read/Write
The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration
purposes.
The timing of the Burst mode DMA data transfer is found in the Timing Diagrams section of this data sheet.
The basic sequence of operation is as follows:
The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration
purposes.
Signal
Signal
nDACK
nDACK
DREQ
DREQ
nDACK becomes active (low) upon DREQ becoming active (high) and catching the host bus (AEN=
“1”).
DREQ becomes inactive after TC asserts (when nDACK= “0”). In this case, DREQ doesn't become
active again after nDACK becomes inactive.
nDACK becomes inactive after DREQ= 0 and the present cycle finishes.
TC
TC
Figure 5.6
Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing
- Burst Mode DMA Data Transfer Rough Timing
DATASHEET
Page 23
Revision 09-27-07