COM20022I-HT SMSC, COM20022I-HT Datasheet

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... Automatically Detects Type of Microcontroller Interface 2Kx8 On-Chip Dual Port RAM Command Chaining for Packet Queuing Sequential Access to Internal RAM Software Programmable Node ID SMSC COM20022I COM20022I 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Eight, 256 Byte Pages Allow Four Pages TX and ...

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... COM20022ITQFP for 48 pin TQFP package COM20022I-HT for 48 pin, TQFP Lead-Free RoHS Compliant package 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...

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... Setup 2 Register..............................................................................................................................35 6.3 Bus Control Register ..................................................................................................................................36 6.4 DMA Count Register ..................................................................................................................................36 6.5 Internal RAM ..............................................................................................................................................47 6.5.1 Sequential Access Memory.................................................................................................................47 6.5.2 Access Speed .....................................................................................................................................47 6.6 Software Interface ......................................................................................................................................47 6.6.1 Selecting RAM Page Size ...................................................................................................................48 6.6.2 Transmit Sequence .............................................................................................................................49 6.6.3 Receive Sequence ..............................................................................................................................50 SMSC COM20022I Page 3 DATASHEET Revision 09-27-07 ...

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... Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing.................................................................................23 Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing ........................................................................................23 Figure 5.7 - High Speed CPU Bus Timing - Intel CPU Mode .......................................................................................25 Figure 5.8 - COM20022I Network Using RS-485 Differential Transceivers ....................................................................27 Figure 5.9 - Dipulse Waveform for Data of 1-1-0 ...........................................................................................................27 Figure 5.10 - Internal Block Diagram.............................................................................................................................28 Figure 6 ...

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... Table 6.12 - Bus Control Register.................................................................................................................................45 Table 6.13 - DMA Count Register.................................................................................................................................46 Table 8.1 - DMA Timing................................................................................................................................................76 Table 9.1 - COM20022I 48 Pin TQFP Package Parameters........................................................................................78 For more details on the ARCNET protocol engine and traditional dipulse signaling schemes, please refer to the ARCNET Local Area Network Standard, or the ARCNET Designer's Handbook, available from Datapoint Corporation ...

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... ARCNET protocol engine. interfaces, eight- page message support, and extended temperature range of the COM20022I make it the only true network controller optimized for use in industrial, embedded, and automotive applications. Using an ARCNET protocol engine is the ideal solution for embedded control applications because it provides a deterministic token-passing protocol, a highly reliable and proven networking scheme, and a data rate Mbps when using the COM20022I ...

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... Commercial: 0°C to +70° Industrial: -40°C to +85° Industrial: -40°C to +85°C DEVICE TYPE: 20022I = Universal Local Area Network Controller DEVICE TYPE: 20022 = Universal Local Area Network Controller (with RAM) (with RAM) Figure 2.1 - COM20022I Pin Configuration Page 7 DATASHEET nCS ...

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... High, this signal is connected to internal pull-up registers IN Terminal Count signal. Active polarity is programmable. Default is active high. When BUSTMG is High, this signal is connected to the internal pull-up resistor. IN Refresh execution signal. Falling edge detection. This signal is connected to the internal pull-up resistor. Page 8 DATASHEET Datasheet DESCRIPTION SMSC COM20022I ...

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... Ground VSS 18,23, 30,41 19,27 N/C N/C SMSC COM20022I I/O TRANSMISSION MEDIA INTERFACE OUT In Normal Mode, these active low signals carry the transmit data information, encoded in pulse format as DIPULSE waveform. In Backplane Mode, the nPULSE1 signal driver is programmable (push/pull or open-drain), while the ...

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... No OK? Increment Y N Activity NID Y for 18.7 us? LENGTH OK? Y DID =0? N DID =ID? Y SEND ACK COM20022I Operation Figure 3.1 - Page 10 DATASHEET Datasheet Activity for 20.5 uS Set NID=ID N Broadcast Enabled? Start Timer: Y T=(255-ID) x 36.5 us Activity Y On Line T= Set RI N SMSC COM20022I ...

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... Data Rates The COM20022I is capable of supporting data rates from 156.25 Kbps to 10 Mbps. The following protocol description assumes a 10 Mbps data rate. To attain the faster data rates, the clock frequency may be doubled or quadrupled by the internal clock multiplier (see next section). For slower data rates, an internal clock divider scales down the clock frequency ...

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... COM20022I releases control of the line. INVITATIONS TO TRANSMIT are sent to all NIDs (1-255). Each COM20022I on the network will finally have saved a NID value equal to the ID of the COM20022I that it released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS TO TRANSMIT being sent to ID's not on the network, until the next NETWORK RECONFIGURATION occurs ...

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... COM20022I to start sending a message in response to a received message) which is approximately 3.2 μS. The round trip propagation delay is a function of the transmission media and network topology. For a typical system using RG62 coax in a baseband system, a one way cable propagation delay of 7.75 μ ...

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... Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X ALERT SOH SID BURST Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM ALERT EOT DID BURST ALERT ENQ DID BURST DID DID COUNT data Page 14 DATASHEET Datasheet DID DID data CRC CRC SMSC COM20022I + 1. ...

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... An ACK (ACKnowledgement--ASCII code 86H) character 4.6.5 Negative Acknowledgements A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character SMSC COM20022I ALERT BURST ACK ALERT BURST NAK Page 15 DATASHEET ...

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... COM20022I. The signal on the A0 pin during the odd location access tells the COM20022I the type of bus. Since multiplexed operation requires active low, activity on the A0 line tells the COM20022I that the bus is non- multiplexed. The device defaults to multiplexed operation. Both determinations may be made simultaneously by performing a WRITE followed by a READ operation to an odd location within the COM20022I Address space 20022 registers ...

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... GND nINTR Differential Driver Configuration Media Interface * XTAL1 XTAL2 A0/nMUX may be replaced with Figure MHz XTAL +5V RXIN 100 Ohm nPULSE1 NOTE: COM20022I must be in backplane FIGURE B Page 17 DATASHEET 75176B or Equiv. +5V 2 Receiver 6 HFD3212-002 7 Transmitter HFE4211-014 3 + Fiber Interface (ST Connectors) Revision 09-27-07 ...

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... HYC9088 RXIN 12 N/C 11 5.6K nPULSE1 1/2W 5.6K nPULSE2 1/2W 17, 19 Traditional Hybrid 0.47 Configuration uF - *Valid for 2.5 Mbps only. uF FIGURE C Page 18 DATASHEET Datasheet 75176B or Equiv. Differential Driver Configuration * Media Interface may be replaced with Figure 0.01 uF 1KV SMSC COM20022I ...

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... The interface to the internal RAM is software selectable as either 8 or 16-bit. This feature is new to the COM20022I. The D15-D8 pins are the upper-byte data bus pins. The nIOCS16 pin is the 16-bit I/O access enable output pin. This pin is active low for a 16-bit RAM access by the CPU (not a DMA access). ...

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... The nDACK pin is asserted by the DMA Controller detecting the DREQ pin asserted. 2. The DREQ pin is deasserted by the COM20022I detecting the nDACK pin asserted. 3. The nDACK pin is deasserted by the DMA Controller detecting the DREQ pin deasserted after executing the present read or write cycle. ...

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... DMA cycles is approximately 1uS. The DMA overhead time is approximately 2.5μS. The Refresh execution time is 500nS. This computes to 15μS - 2.5μS - 500nS = 12μ cycles. Therefore the DREQ pin must be negated every 12 cycles. Figure 5.4 illustrates the rough timing of the Programmable- Burst mode DMA transfer. SMSC COM20022I minimum 4T ARB Writing Address ...

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... DREQ doesn't become active again after nDACK becomes inactive. nDACK becomes inactive after DREQ=0 and the present cycle finishes. Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Transfer term (Counting Read/Write pulse or counting internal timer) Page 22 DATASHEET Datasheet Gate Time Restart Transfer SMSC COM20022I ...

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... DREQ= 0 and the present cycle finishes. The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration purposes. DREQ nDACK Read/Write Signal TC - Burst Mode DMA Data Transfer Rough Timing Figure 5.6 SMSC COM20022I Page 23 DATASHEET Revision 09-27-07 ...

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... High Speed CPU Bus Timing Support High speed CPU bus support was added to the COM20022I. The reasoning behind this is as follows: With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read signal is active and remain after the read signal is inactive. But the High Speed CPU bus timing doesn't adhere to these timings ...

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... Transmission Media Interface The bottom halves of Figure 5.1 and Figure 5.2 illustrate the COM20022I interface to the transmission media used to connect the node to the network. Table 5.1 lists different types of cable which are suitable for ARCNET applications. The user may interface to the cable of choice in one of three ways: ...

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... RF transformer of the LAN Driver, which produces a positive pulse at the RXIN pin of the COM20022I. The pulse on the RXIN pin represents a logic "1". Lack of pulse represents a logic "0". Typically, RXIN pulses occur at multiples of 400nS. The COM20022I can tolerate distortion of plus or minus 100nS and still correctly capture and convert the RXIN pulses to NRZ format ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Datasheet RT 75176B or Equiv. COM20022I - COM20022I Network Using RS-485 Differential Transceivers Figure 5.8 20MHZ CLOCK (FOR REF. ONLY) 100ns nPULSE1 100ns nPULSE2 200ns DIPULSE RXIN Figure 5.9 In typical applications, the serial backplane is terminated at both ends and a bias is provided by the external pull-up resistor ...

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... COM20022I. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is active. The nPULSE1 signal issues a 200nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lack of pulse indicates a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20022I is disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive. ...

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... RG-59/U Belden #89108 RG-11/U Belden #89108 IBM Type 1* Belden #89688 IBM Type 3* Telephone Twisted Pair Belden #1155A COMCODE 26 AWG Twisted Pair Part #105-064-703 Note*: Non-plenum-rated cables of this type are also available. SMSC COM20022I Table 5.1 - Typical Media NOMINAL IMPEDANCE 93 Ω 75 Ω 75 Ω ...

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... The COM20022I derives a 20 MHz and a 10 MHz clock from the output clock of the Clock Multiplier. These clocks provide the rate at which the instructions are executed within the COM20022I. The 20 MHz clock is the rate at which the program counter operates, while the 10 MHz clock is the rate at which the instructions are executed ...

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... TIM6/ CYC7 CYC6 Note*: This bit can be written and read. *DATA REGISTER AT 16 BIT ACCESS BIT BIT BIT BIT REGISTER DATA SMSC COM20022I Table 6.1 - Read Register Summary READ X/TA POR TEST RECON RCV- TOKEN EXC- TENTID ACT NAK X X DMA ...

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... Interrupt Mask Register (IMR) The COM20022I is capable of generating an interrupt signal when certain status bits become true. A write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic " ...

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... Node ID. Refer to the Initialization Sequence section for further detail on the use of the DUPID bit. The core of the COM20022I does not wake up until a Node ID other than zero is written into the Node ID Register. During this time, no microcode is executed, no tokens are passed by this node, and no reconfigurations are caused by this node ...

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... Status Register The COM20022I Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20022I, the COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration Register ...

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... MHz crystal. The RBUSTMG bit is used to Disable/Enable Fast Read function for High Speed CPU bus support. The EF bit is used to enable the new timing for certain functions in the COM20022I ( the timing is the same as in the COM20020 Rev. B). See Appendix “A”. The NOSYNC bit is used to enable the NOSYNC function during initialization ...

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... Bus Control Register The Bus Control Register is new to the COM20022I 8-bit read/write register accessed when the Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register). This register contains bits for control of the DMA functionality. The DRQPOL bit is used to set the active polarity of the DREQ pin ...

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... NAK. These bits are undefined. This bit, if high, indicates that the COM20022I has been reset by either a software reset, a hardware reset, or writing 00H to the Node ID Register. The POR bit is cleared by the "Clear Flags" command. ...

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... Reading the Diagnostic Status Register does not clear this bit. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set. The bit is cleared by reading the Next ID Register. These bits are undefined. Page 38 DATASHEET Datasheet SMSC COM20022I ...

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... If "c" logic "0", the device handles only short packets. This command resets certain status bits of the COM20022I. A logic "1" on "p" resets the POR status bit and the EXCNAK Diagnostic status bit. A logic "1" on "r" resets the RECON status bit. ...

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... Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Table 6.6 - Address Pointer High Register This bit tells the COM20022I whether the following access will be a read or write. A logic "1" prepares the device for a read, a logic "0" prepares it for a write. ...

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... Reserved 2,1,0 Sub Address 2,1,0 SUBAD 2,1,0 SMSC COM20022I Table 6.7 - Address Pointer Low Register These bits hold the lower 8 address bits which provide the addresses to RAM. When 16 bit access is enabled, (W16=1), A0 becomes the SWAP bit. Swap bit is undefined after a hardware reset. The swap bit must be set before W16 bit is set to “ ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Table 6.9 - Configuration Register DESCRIPTION A software reset of the COM20022I is executed by writing a logic "1" to this bit. A software reset does not reset the microcontroller interface mode, nor does it affect the Configuration Register. The only registers that the software reset affect are the Status Register, the Next ID Register, and the Diagnostic Status Register. This bit must be brought back to logic " ...

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... ID. This feature can be used to put the COM20022I in a 'listen-only' mode, where the transmitter is disabled and the COM20022I is not passing tokens. Defaults low. These bits are used to determine the data rate of the COM20022I. The following table is for a 20 MHz crystal: (Clock Multiplier is bypassed) ...

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... Start initializing routine (Execute existing software) This bit is used to enable the new enhanced functions in the COM20022I Disable (Default Enable the timing and function is the same as in the COM20020, Revision B. See appendix “A”. EF bit must be ‘1’ if the data rate is over 5Mbps. EF bit should be ‘ ...

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... TC Polarity TCPOL 0 DREQ Polarity DRQPOL SMSC COM20022I DESCRIPTION These bits are used to program the reconfiguration timer as a function of maximum node count. These bits set the time out period of the reconfiguration timer as shown below. The time out periods shown are for 10 Mbps. ...

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... CYC7-CYC0 all zeroes means 256 cycles illegal) Data Register I/O Address 04H Memory Data Bus 8 Address Pointer Register I/O Address 03H Low Memory Address Bus 11-Bit Counter 11 - Sequential Access Operation Page 46 DATASHEET Datasheet DESCRIPTION INTERNAL RAM SMSC COM20022I ...

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... Internal RAM The integration of the RAM in the COM20022I represents significant real estate savings. The most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and control functions which were necessary to interface to the RAM ...

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... Please note that it is the responsibility of software to reserve 512 bytes for each receive page if the device is configured to handle long packets. The COM20022I does not check page boundaries during reception. If the device is configured to handle only short packets, then both transmit and receive pages may be allocated as 256 bytes long, freeing at least 1KByte at any given time ...

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... The SID in Address 0 is used by the receiving node to reply to the transmitting node. The COM20022I puts the local ID in this location, therefore it is not necessary to write into this location. Please note that a short packet may contain between 1 and 253 data bytes, while a long packet may contain between 257 and 508 data bytes ...

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... These situations can be determined by either using the improved diagnostic features of the COM20022I or using another software timeout which is greater than the worst case time for a round trip token pass, which occurs when all nodes transmit a maximum length message. ...

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... RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected buffer, the COM20022I sets the RI bit to logic "1" to signal the microcontroller that the reception is complete. MSB ...

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... Register will again be updated with the results of the second reception and a second interrupt resulting from the second reception will occur. In the COM20022I, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon Revision 09-27-07 10 Mbps ARCNET (ANSI 878 ...

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... Setup1 Register should be written before the Node ID Register. Once the Node ID Register is written to, the COM20022I reads the value and executes two write cycles to the RAM buffer. Address 0 is written with the data D1H and address 1 is written with the Node ID. The data pattern D1H was chosen arbitrarily, and is meant to provide assurance of proper microsequencer operation ...

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... Tentative ID. To determine the next logical node, the software should read the Next ID Register. 6.10 Improved Diagnostics The COM20022I allows the user to better manage the operation of the network through the use of the internal Diagnostic Status Register. A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this node expired, causing a reconfiguration by this node ...

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... If an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No external resistor is required, since the COM20022I contains an internal resistor. The crystal must have an accuracy of 0.020% or better. The oscillation frequency range is from 10 MHz to 20 MHz. ...

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... High Input Voltage 1 (All inputs except A2, XTAL1, nRESET, nRD, nWR, nREFEX and RXIN) Low Input Voltage 2 (XTAL1) High Input Voltage 2 (XTAL1) Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM COM20022II +85 A SYMBOL MIN TYP V IL1 V 2.0 IH1 V IL2 V 4 ...

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... Supply DD Current Input Pull-up Current (nPULSE1 in Open-Drain Mode, A1, AD0-AD2, D3-D15, nREFEX, (nDACK and TC in BUSTMG = H)) Input Leakage Current (All inputs except A1, AD0-AD2, D3-D15, XTAL1, XTAL2, nREFEX, (nDACK and TC in BUSTMG = H)) SMSC COM20022I SYMBOL MIN TYP V 1.8 ILH V 1.2 IHL V OL1 V 2.4 ...

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... Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM = 1MHz 0V MIN TYP MAX C 5 OUT1 400 OUT2 Outputs: t 2.0V 0.8V 2.0V 0.8V t Page 58 DATASHEET Datasheet UNIT COMMENT pF pF Maximum Capacitive Load which can be supported by each output. pF SMSC COM20022I ...

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... Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle Figure 8.1 SMSC COM20022I VALID DATA VALID t1 t2, t4 ...

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... Note 3 t15 t14 Invalid Valid Value Parameter 4T to nRD Low if SLOW ARB = 0 opr if SLOW ARB = 1 from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 60 DATASHEET Datasheet t7 t8 t12 Note 2 min max units ARB SMSC COM20022I ...

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... Write cycle for Address Pointer Low Register occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. - Multiplexed Bus, 68XX-Like Control Signals Write Cycle Figure 8.3 SMSC COM20022I VALID DATA t2, t4 t12 t5 ...

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... MUST BE: BUSTMG pin = HIGH min Parameter Next )** * 4T ARB from the trailing edge of nWR to the leading edge of the ARB from the trailing edge of nWR to the ARB from the trailing edge of nRD to the ARB Page 62 DATASHEET Datasheet t7 Note 2 t8** t8 t12 max units SMSC COM20022I ...

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... Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Notes 2 and 3 are applied to an access to Data Register by DMA transfer. - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle Figure 8.5 SMSC COM20022I VALID t1 t3 Note 3 t5 ...

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... CASE 2: BUSTMG pin = LOW or RBUSTMG bit = 1 Parameter 4T to nRD Low if SLOW ARB = 0 opr if SLOW ARB = 1 opr from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 64 DATASHEET Datasheet Note 2 t7 t12 min max units *+30 nS ARB nS 60 100 40*** nS 0**** SMSC COM20022I ...

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... Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle Figure 8.7 SMSC COM20022I VALID ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM VALID t10 t8 VALID DATA t12 VALID VALUE Parameter 4T if SLOW ARB = 0 opr if SLOW ARB = 1 from the trailing edge of nDS to ARB Page 66 DATASHEET Datasheet t11 Note 2 t9 t13 min max units - *+30 nS ARB 100 40*** 0**** nS SMSC COM20022I ...

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... Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Notes 2 and 3 are applied to an access to Data Register by DMA transfer. Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle SMSC COM20022I VALID t1 t3 Note 3 ...

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... CASE 2: BUSTMG pin = LOW min Next ) 4T * ARB 0***** if SLOW ARB = 0 from the trailing edge of nWR to the leading edge of the ARB from the trailing edge of nWR to the ARB from the trailing edge of nRD to the ARB Page 68 DATASHEET Datasheet t5** Note 2 t12 t7 max units 40**** nS nS SMSC COM20022I ...

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... Write cycle for Address Pointer Low Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle Figure 8.11 SMSC COM20022I t12 VALID VALUE VALID t1 t3 ...

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... VALID DATA CASE 2: BUSTMG pin = LOW min Next )** * 4T ARB 0***** if SLOW ARB = 0 from the trailing edge of nDS to the leading edge ARB from the trailing edge of nDS to ARB Page 70 DATASHEET Datasheet t13 t11 Note 2 t6 max units 40**** nS nS SMSC COM20022I ...

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... Low to nPULSE1 Low t5 Beginning of Last Bit Time to nTXEN High t6 RXIN Active Pulse Width t7 RXIN Period t8 RXIN Inactive Pulse Width Note: Use Only 2.5 Mbps Figure 8.13 - Normal Mode Transmit or Receive Timing (These signals are to and from the hybrid) SMSC COM20022I Parameter Page 71 DATASHEET t5 ...

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... Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM t10 t12 t11 Parameter Page 72 DATASHEET Datasheet t13 t8 LAST BIT (400 nS BIT TIME) min typ max units - 200* nS 400 100* nS 100* nS 200 -25 650 750 nS 450 550 nS 10 200* nS 400 SMSC COM20022I ...

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... High to Next nINTR Low Note period of external XTAL oscillation frequency. XTL Note**: T is period of Data Rate (i.e. at 2.5 Mbps Note***: When the power is turned on measured from stable XTAL oscillation after V DD Figure 8.16 SMSC COM20022I t2 t3 1.0V min -200 + - - TTL Input Timing on XTAL1 Pin ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM t20 t19 t26 t21 t4 t1 t24 t25 t15 t11 t16 t12 t14 t9 t8 VALID - DMA Timing (Intel Mode 80XX) Page 74 DATASHEET Datasheet t19 t20 t7* t24 t25 t13 t18 t17 VALID SMSC COM20022I ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Datasheet nCS t10 nREFEX t3 DREQ t2 nDACK TC DIR nDS Write LOW-POINTER when DMAEN=1 DATA (D15-D0) Note measured from the latest active timing among TC, Write/Read. Figure 8.18 SMSC COM20022I t20 t19 t26 t21 t4 t1 t24 t25 t15 t16 VALID t11 t22 t23 ...

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... Page 76 DATASHEET Datasheet MAX UNIT NOTE 5Tarb Note 1 +40ns 40 ns Note Note 4 8Txtl Note 2 +40ns 16Txtl +40ns 40 ns Note Note Note Note Note 4 Note 4 Note 4 ns Note 4,5 ns Note 1,4 Note 1,4,5 ns Note 4 ns Note Note 4 ns Note 4 Note 2 SMSC COM20022I ...

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... At MOTOROLA MODE, write signal is nDS when DIR is Low and the read signal is nDS when DIR is High. 5. Conditions of CASE1W, CASE2W, CASE1R and CASE2R are shown below; CASE1W : BUSTMG pin = High CASE2W : BUSTMG pin = Low CASE1R : BUSTMG pin = High and RBUSTMG bit = 0 CASE2R : BUSTMG pin = Low or RBUSTMG bit = 1 SMSC COM20022I Page 77 DATASHEET Revision 09-27-07 ...

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... Chapter 9 Package Outline Figure 9.1 - COM20022I 48 Pin TQFP Package Outline Table 9.1 - COM20022I 48 Pin TQFP Package Parameters MIN NOMINAL 0.05 A2 1.35 D 8.80 D/2 4.40 D1 6.90 E 8.80 E/2 4.40 E1 6.90 H 0. 0.50 Basic θ 0.17 R1 0.08 R2 0.08 ccc ~ ccc ~ Notes: 1. Controlling Unit: millimeter 2. Tolerance on the position of the leads is ± ...

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... RAM initialization sequence to be written. The following discussion describes the function of this bit: During initialization, after the CPU writes the Node ID, the COM20022I will write "D1"h data to Address 000h and Node-ID to Address 001h of its internal RAM within 3uS. These values are read as part of the diagnostic test ...

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... Shorten The Write Interval Time To The Command Register The COM20022I limits the write interval time for continuous writing to the Command register. The minimum interval time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 μ the 156.25 Kbps. This 1.6 μ very long for CPU. ...

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... Tentative-ID register is written, the effect of the old Tentative-ID remains active for a while, which results in an incorrect network map. It can be avoided by a carefully coded software routine, but this requires the programmer to have deep knowledge of how the COM20022I works. Duplicate-ID is mainly used for generating the Network MAP. This has the same issue as Tentative-ID. ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM LS688x nG 12 bit Comparator P Q I/O Address Seeting (DIP P=Q 12 LS245x A 16 bit Transceiver DIR 3 Schmitt-Trigger Open-Collector Page 82 DATASHEET Datasheet COM2002I nCS D15-D0 nRD nWR A2-A0 nINTR nIOCS16 DREQ nDACK TC nREFEX nRESET SMSC COM20022I ...