COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet

Page 1

... Automatically Detects Type of Microcontroller Interface 2Kx8 On-Chip Dual Port RAM Command Chaining for Packet Queuing Sequential Access to Internal RAM Software Programmable Node ID SMSC COM20022I COM20022I 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Eight, 256 Byte Pages Allow Four Pages TX and ...

Page 2

... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“ ...

Page 3

... Setup 2 Register..............................................................................................................................35 6.3 Bus Control Register ..................................................................................................................................36 6.4 DMA Count Register ..................................................................................................................................36 6.5 Internal RAM ..............................................................................................................................................47 6.5.1 Sequential Access Memory.................................................................................................................47 6.5.2 Access Speed .....................................................................................................................................47 6.6 Software Interface ......................................................................................................................................47 6.6.1 Selecting RAM Page Size ...................................................................................................................48 6.6.2 Transmit Sequence .............................................................................................................................49 6.6.3 Receive Sequence ..............................................................................................................................50 SMSC COM20022I Page 3 DATASHEET Revision 09-27-07 ...

Page 4

... Figure 8.16 - Reset and Interrupt Timing .....................................................................................................................73 Figure 8.17 - DMA Timing (Intel Mode 80XX) ..............................................................................................................74 Figure 8.18 - DMA Timing (Motorola Mode 68XX) .......................................................................................................75 Figure 9.1 - COM20022I 48 Pin TQFP Package Outline..............................................................................................78 Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Page 4 DATASHEET Datasheet SMSC COM20022I ...

Page 5

... Table 9.1 - COM20022I 48 Pin TQFP Package Parameters........................................................................................78 For more details on the ARCNET protocol engine and traditional dipulse signaling schemes, please refer to the ARCNET Local Area Network Standard, or the ARCNET Designer's Handbook, available from Datapoint Corporation. SMSC COM20022I Page 5 DATASHEET Revision 09-27-07 ...

Page 6

... Chapter 1 General Description SMSC's COM20022I is a member of the family of Embedded ARCNET Controllers from Standard Microsystems Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in industrial, automotive, and embedded control environments using an ARCNET protocol engine. interfaces, eight- page message support, and extended temperature range of the COM20022I make it the only true network controller optimized for use in industrial, embedded, and automotive applications ...

Page 7

... AD1 3 D10 AD2 4 D11 5 6 VSS VDD VSS Ordering Information: COM20022 SMSC COM20022I COM20022I COM20022 48 Pin TQFP 48 Pin TQFP Ordering Information: COM20022I PACKAGE TYPE: TQFP PACKAGE TYPE: TQFP TEMP RANGE: (Blank) = Commercial 0° 70° TEMP RANGE: (Blank) = Commercial: 0°C to +70° Industrial: -40° ...

Page 8

... High, this signal is connected to internal pull-up registers IN Terminal Count signal. Active polarity is programmable. Default is active high. When BUSTMG is High, this signal is connected to the internal pull-up resistor. IN Refresh execution signal. Falling edge detection. This signal is connected to the internal pull-up resistor. Page 8 DATASHEET Datasheet DESCRIPTION SMSC COM20022I ...

Page 9

... Ground VSS 18,23, 30,41 19,27 N/C N/C SMSC COM20022I I/O TRANSMISSION MEDIA INTERFACE OUT In Normal Mode, these active low signals carry the transmit data information, encoded in pulse format as DIPULSE waveform. In Backplane Mode, the nPULSE1 signal driver is programmable (push/pull or open-drain), while the ...

Page 10

... No OK? Increment Y N Activity NID Y for 18.7 us? LENGTH OK? Y DID =0? N DID =ID? Y SEND ACK COM20022I Operation Figure 3.1 - Page 10 DATASHEET Datasheet Activity for 20.5 uS Set NID=ID N Broadcast Enabled? Start Timer: Y T=(255-ID) x 36.5 us Activity Y On Line T= Set RI N SMSC COM20022I ...

Page 11

... INTERNAL CLOCK CLOCK PRESCALER FREQUENCY 80 MHz Div MHz Div MHz Div Div Div Div Div. by 128 SMSC COM20022I TIMEOUT SCALING FACTOR DATA RATE 10 Mbps 5 Mbps 2.5 Mbps 1.25 Mbps 625 Kbps 312.5 Kbps 156.25 Kbps Page 11 DATASHEET If the packet is received (MULTIPLY BY) ...

Page 12

... INVITATION TO TRANSMIT to an incremented ID and eventually a response will be received. Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM CLOCK FREQUENCY (DATA RATE MHz (Up to 2.5Mbps) Default (Bypass MHz (Up to 5Mbps) 0 Reserved 1 80 MHz (Only 10Mbps) During NETWORK RECONFIGURATION, Page 12 DATASHEET Datasheet SMSC COM20022I ...

Page 13

... COM20022I can operate by controlling the three timeout values described above. For proper network operation, all COM20022I's connected to the same network must have the same Response Time, Idle Time, and Reconfiguration Time. SMSC COM20022I Page 13 DATASHEET Revision 09-27-07 ...

Page 14

... Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X ALERT SOH SID BURST Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM ALERT EOT DID BURST ALERT ENQ DID BURST DID DID COUNT data Page 14 DATASHEET Datasheet DID DID data CRC CRC SMSC COM20022I + 1. ...

Page 15

... An ACK (ACKnowledgement--ASCII code 86H) character 4.6.5 Negative Acknowledgements A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character SMSC COM20022I ALERT BURST ACK ALERT BURST NAK Page 15 DATASHEET ...

Page 16

... Whenever the pointer is loaded for reads with a new value, data is immediately prefetched to prepare for the first read operation. Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Once the type of bus is determined, the COM20022I Page 16 DATASHEET Datasheet The SMSC COM20022I ...

Page 17

... A15 RESET nRD nWR nINT1 8051 RXIN TXEN nPULSE1 nPULSE2 GND BACKPLANE CONFIGURATION FIGURE A - Multiplexed, 8051-Like Bus Interface with RS-485 Interface Figure 5.1 SMSC COM20022I COM2002I AD0-AD2, D3-D7 A2/BALE RXIN nCS nRESET nTXEN nPULSE1 nRD/nDS nPULSE2 nWR/DIR GND nINTR Differential Driver ...

Page 18

... HYC9088 RXIN 12 N/C 11 5.6K nPULSE1 1/2W 5.6K nPULSE2 1/2W 17, 19 Traditional Hybrid 0.47 Configuration uF - *Valid for 2.5 Mbps only. uF FIGURE C Page 18 DATASHEET Datasheet 75176B or Equiv. Differential Driver Configuration * Media Interface may be replaced with Figure 0.01 uF 1KV SMSC COM20022I ...

Page 19

... DREQ pin; the TCPOL bit sets the active polarity of the TC pin; the DMAMD[1,0] bits select the data transfer mode of the DMA. The ITCEN/RTRG bit has one of two functions, depending on the DMA transfer mode selected. ITCEN is the Internal Terminal Counter Enable used to select whether the DMA is terminated by external TC SMSC COM20022I SWAP BIT (NOTE) D15-D8 PINS 0 ...

Page 20

... The DREQ pin stays asserted until the TC pin goes High. In Programmable-Burst mode, the gating can be by timer or by cycle counter. Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Page 20 DATASHEET Datasheet time after writing the ARB time after writing the ARB SMSC COM20022I ...

Page 21

... DMA cycles is approximately 1uS. The DMA overhead time is approximately 2.5μS. The Refresh execution time is 500nS. This computes to 15μS - 2.5μS - 500nS = 12μ cycles. Therefore the DREQ pin must be negated every 12 cycles. Figure 5.4 illustrates the rough timing of the Programmable- Burst mode DMA transfer. SMSC COM20022I minimum 4T ARB Writing Address ...

Page 22

... DREQ doesn't become active again after nDACK becomes inactive. nDACK becomes inactive after DREQ=0 and the present cycle finishes. Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Transfer term (Counting Read/Write pulse or counting internal timer) Page 22 DATASHEET Datasheet Gate Time Restart Transfer SMSC COM20022I ...

Page 23

... DREQ= 0 and the present cycle finishes. The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration purposes. DREQ nDACK Read/Write Signal TC - Burst Mode DMA Data Transfer Rough Timing Figure 5.6 SMSC COM20022I Page 23 DATASHEET Revision 09-27-07 ...

Page 24

... By this modification, the internal real address and Chip Select are stable while the internal real read signal is active. Refer to Figure 5.7 on the following page. Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Page 24 DATASHEET Datasheet SMSC COM20022I ...

Page 25

... The bottom halves of Figure 5.1 and Figure 5.2 illustrate the COM20022I interface to the transmission media used to connect the node to the network. Table 5.1 lists different types of cable which are suitable for ARCNET applications. The user may interface to the cable of choice in one of three ways: SMSC COM20022I VALID VALID ...

Page 26

... Hybrid offers isolation for the safety of the system and offers high Common Mode Rejection. The Traditional Hybrid Interface uses circuits like SMSC's HYC9068 or HYC9088 to transfer the pulse-encoded data between the cable and the COM20022I. The COM20022I transmits a logic "1" by generating two 100nS non-overlapping negative pulses, nPULSE1 and nPULSE2. Lack of pulses indicates a logic " ...

Page 27

... When the device is in Backplane Mode, the clock provided by the nPULSE2 signal may be used for encoding the data into a different encoding scheme or other synchronous operations needed on the serial data stream. SMSC COM20022I +VCC +VCC ...

Page 28

... RAM STATUS/ COMMAND REGISTER MICRO- SEQUENCER AND WORKING REGISTERS OSCILLATOR RECONFIGURATION NODE ID LOGIC TIMER - Internal Block Diagram Figure 5.10 Page 28 DATASHEET Datasheet coupled The polarity ADDITIONAL REGISTERS nPULSE1 nPULSE2 TX/RX nTXEN LOGIC RXIN XTAL1 XTAL2 DREQ nDACK DMA TC nREFEX SMSC COM20022I ...

Page 29

... RG-59/U Belden #89108 RG-11/U Belden #89108 IBM Type 1* Belden #89688 IBM Type 3* Telephone Twisted Pair Belden #1155A COMCODE 26 AWG Twisted Pair Part #105-064-703 Note*: Non-plenum-rated cables of this type are also available. SMSC COM20022I Table 5.1 - Typical Media NOMINAL IMPEDANCE 93 Ω 75 Ω 75 Ω ...

Page 30

... The COM20022I contains an internal reconfiguration timer which interrupts the microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of the Diagnostic Status Register is set. Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Page 30 DATASHEET Datasheet SMSC COM20022I ...

Page 31

... TIM6/ CYC7 CYC6 Note*: This bit can be written and read. *DATA REGISTER AT 16 BIT ACCESS BIT BIT BIT BIT REGISTER DATA SMSC COM20022I Table 6.1 - Read Register Summary READ X/TA POR TEST RECON RCV- TOKEN EXC- TENTID ACT NAK X X DMA ...

Page 32

... AD0 URATION TID1 TID0 TENTID NODEID NID1 NID0 CKP1 SLOW- SETUP1 ARB 0 0 TEST RCN- RCN- SETUP2 TM1 TM0 TC- DRQ- BUS POL POL CONTROL TC1/ TC0/ DMA COUNT TIM1/ TIM0/ CYC1 CYC0 BIT BIT BIT BIT BIT BIT ADDR SMSC COM20022I 04 ...

Page 33

... While the Transmitter is disabled, the Receiver portion of the device is still functional and will provide the user with useful information about the network. The Node ID Register defaults to the value 0000 0000 upon hardware reset only. SMSC COM20022I Page 33 DATASHEET DMAEND bit is ...

Page 34

... The COM20022I Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20022I, the COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration Register ...

Page 35

... RCNTM1 RCNTM0 Note 6.1 The node ID value 255 must exist in the network for the 13.125 mS time-out to be valid. SMSC COM20022I If this bit is reset, the line has to be idle for the RAM TIME-OUT PERIOD 0 210 26. ...

Page 36

... Programmable-Burst by Timer mode. The CYC7-CYC0 bits are for setting the cycle count value of the continuous DMA transfer in Programmable-Burst by cycle mode. Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM DREQ nDACK nWR/nRD Page 36 DATASHEET Datasheet RTRG=1 350/750ns SMSC COM20022I ...

Page 37

... Acknowledged 0 Transmitter TA Available SMSC COM20022I Table 6.3 - Status Register DESCRIPTION This bit, if high, indicates that the receiver is not enabled because either an "Enable Receive to Page fnn" command was never issued packet has been deposited into the RAM buffer page fnn as specified by the last " ...

Page 38

... Reading the Diagnostic Status Register does not clear this bit. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set. The bit is cleared by reading the Next ID Register. These bits are undefined. Page 38 DATASHEET Datasheet SMSC COM20022I ...

Page 39

... Start Internal Operation 0001 0000 Clear Mask bit of DMAEND SMSC COM20022I Table 6.5 - Command Register DESCRIPTION This command is used only in the Command Chaining operation. Please refer to the Command Chaining section for definition of this command. This command will cancel any pending transmit command (transmission that has not yet started) and will set the TA (Transmitter Available) status bit to logic " ...

Page 40

... DAMEN is the Interrupt source signal DMAEND. The DMAEN bit is cleared automatically by finishing the DMA. If the DMAEND bit in the Mask register is not masked, the Interrupt occurs by finishing the DMA operation. These bits hold the upper three address bits which provide addresses to RAM. Page 40 DATASHEET Datasheet DESCRIPTION SMSC COM20022I ...

Page 41

... Reserved 2,1,0 Sub Address 2,1,0 SUBAD 2,1,0 SMSC COM20022I Table 6.7 - Address Pointer Low Register These bits hold the lower 8 address bits which provide the addresses to RAM. When 16 bit access is enabled, (W16=1), A0 becomes the SWAP bit. Swap bit is undefined after a hardware reset. The swap bit must be set before W16 bit is set to “ ...

Page 42

... This bit, if high, enables the Command Chaining operation of the device. Please refer to the Command Chaining section for further details. A low level on this bit ensures software compatibility with previous SMSC ARCNET devices. When low, this bit disables transmissions by keeping nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN pin inactive. ...

Page 43

... Clock Prescaler Bits 3,2,1 0 Slow Arbitration SLOWARB Select SMSC COM20022I Table 6.10 - Setup 1 Register DESCRIPTION This bit determines the type of PULSE1 output driver used in Backplane Mode. When high, a push/pull output is used. When low, an open drain output is used. The default is open drain. ...

Page 44

... NOSYNC= 0, Enable (Default) The line must be idle for the RAM initialization sequence to be written. NOSYNC= 1, Disable:) The line does not have to be idle for the RAM initialization sequence to be written. See appendix “A”. Page 44 DATASHEET Datasheet Clock Frequency (Data Rate) SMSC COM20022I ...

Page 45

... TC Polarity TCPOL 0 DREQ Polarity DRQPOL SMSC COM20022I DESCRIPTION These bits are used to program the reconfiguration timer as a function of maximum node count. These bits set the time out period of the reconfiguration timer as shown below. The time out periods shown are for 10 Mbps. ...

Page 46

... CYC7-CYC0 all zeroes means 256 cycles illegal) Data Register I/O Address 04H Memory Data Bus 8 Address Pointer Register I/O Address 03H Low Memory Address Bus 11-Bit Counter 11 - Sequential Access Operation Page 46 DATASHEET Datasheet DESCRIPTION INTERNAL RAM SMSC COM20022I ...

Page 47

... Write to Pointer Register Low (this loads the address) Enable Interrupts Read or Write the Data Register (repeat as many times as necessary to empty or fill the buffer) The pointer may now be read to determine how many transfers were completed. SMSC COM20022I Page 47 DATASHEET The Revision 09-27-07 ...

Page 48

... Command Chaining only requires two pages for transmit and two for receive (in this case, a total of four 256 byte pages, leaving 1K free). The general rule which may be applied to determine where in RAM a page begins is as follows: Address = (nn x 512 256). Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Page 48 DATASHEET Datasheet The SMSC COM20022I ...

Page 49

... Command Chaining operation, please see the Command Chaining section for further detail on the transmit sequence. Once the TA bit becomes a logic "1", the microcontroller may issue the "Enable Transmit from Page fnn" command, which resets the TA and TMA bits to logic "0". If the SMSC COM20022I SHORT PACKET LONG PACKET ...

Page 50

... In the latter case, Address 3 contains the value 512-N, where N represents the message length. Note that on reception, Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Page 50 DATASHEET Datasheet SMSC COM20022I ...

Page 51

... Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are pipelined. In order for the COM20022I to be compatible with previous SMSC ARCNET device drivers, the device defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode must be enabled via a logic " ...

Page 52

... In the COM20022I, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Page 52 DATASHEET Datasheet This The COM20022I guarantees a SMSC COM20022I ...

Page 53

... COM20022I compares the value in the Node ID Register with the DID's of the token, and determines whether there is a response to it. Once the Diagnostic Status Register is read, the DUPID bit is cleared. SMSC COM20022I This pulse width is used by the internal digital filter, which XTL. ...

Page 54

... Network and node are operating properly. MYRECON=0, DUPID=0, RCVACT=1, TXEN=0, TOKEN=1: Single node network. Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Once a value is placed in the Tentative ID Register, the Reading the Diagnostic Status Register resets the MYRECON bit. Page 54 DATASHEET Datasheet SMSC COM20022I ...

Page 55

... The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock for other devices. The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390 Ω pull-up resistor is required on XTAL1, while XTAL2 should be left unconnected. SMSC COM20022I Page 55 DATASHEET Revision 09-27-07 ...

Page 56

... Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM COM20022II +85 A SYMBOL MIN TYP V IL1 V 2.0 IH1 V IL2 V 4.0 IH2 Page 56 DATASHEET Datasheet + +150 DD C MAX UNIT COMMENT 0.8 V TTL Levels V TTL Levels 1.0 V TTL Clock Input V SMSC COM20022I +0.3V ...

Page 57

... Supply DD Current Input Pull-up Current (nPULSE1 in Open-Drain Mode, A1, AD0-AD2, D3-D15, nREFEX, (nDACK and TC in BUSTMG = H)) Input Leakage Current (All inputs except A1, AD0-AD2, D3-D15, XTAL1, XTAL2, nREFEX, (nDACK and TC in BUSTMG = H)) SMSC COM20022I SYMBOL MIN TYP V 1.8 ILH V 1.2 IHL V OL1 V 2.4 ...

Page 58

... Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM = 1MHz 0V MIN TYP MAX C 5 OUT1 400 OUT2 Outputs: t 2.0V 0.8V 2.0V 0.8V t Page 58 DATASHEET Datasheet UNIT COMMENT pF pF Maximum Capacitive Load which can be supported by each output. pF SMSC COM20022I ...

Page 59

... Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle Figure 8.1 SMSC COM20022I VALID DATA VALID t1 t2, t4 ...

Page 60

... Note 3 t15 t14 Invalid Valid Value Parameter 4T to nRD Low if SLOW ARB = 0 opr if SLOW ARB = 1 from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 60 DATASHEET Datasheet t7 t8 t12 Note 2 min max units ARB SMSC COM20022I ...

Page 61

... Write cycle for Address Pointer Low Register occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. - Multiplexed Bus, 68XX-Like Control Signals Write Cycle Figure 8.3 SMSC COM20022I VALID DATA t2, t4 t12 t5 ...

Page 62

... MUST BE: BUSTMG pin = HIGH min Parameter Next )** * 4T ARB from the trailing edge of nWR to the leading edge of the ARB from the trailing edge of nWR to the ARB from the trailing edge of nRD to the ARB Page 62 DATASHEET Datasheet t7 Note 2 t8** t8 t12 max units SMSC COM20022I ...

Page 63

... Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Notes 2 and 3 are applied to an access to Data Register by DMA transfer. - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle Figure 8.5 SMSC COM20022I VALID t1 t3 Note 3 t5 ...

Page 64

... CASE 2: BUSTMG pin = LOW or RBUSTMG bit = 1 Parameter 4T to nRD Low if SLOW ARB = 0 opr if SLOW ARB = 1 opr from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 64 DATASHEET Datasheet Note 2 t7 t12 min max units *+30 nS ARB nS 60 100 40*** nS 0**** SMSC COM20022I ...

Page 65

... Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle Figure 8.7 SMSC COM20022I VALID ...

Page 66

... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM VALID t10 t8 VALID DATA t12 VALID VALUE Parameter 4T if SLOW ARB = 0 opr if SLOW ARB = 1 from the trailing edge of nDS to ARB Page 66 DATASHEET Datasheet t11 Note 2 t9 t13 min max units - *+30 nS ARB 100 40*** 0**** nS SMSC COM20022I ...

Page 67

... Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Notes 2 and 3 are applied to an access to Data Register by DMA transfer. Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle SMSC COM20022I VALID t1 t3 Note 3 ...

Page 68

... CASE 2: BUSTMG pin = LOW min Next ) 4T * ARB 0***** if SLOW ARB = 0 from the trailing edge of nWR to the leading edge of the ARB from the trailing edge of nWR to the ARB from the trailing edge of nRD to the ARB Page 68 DATASHEET Datasheet t5** Note 2 t12 t7 max units 40**** nS nS SMSC COM20022I ...

Page 69

... Write cycle for Address Pointer Low Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle Figure 8.11 SMSC COM20022I t12 VALID VALUE VALID t1 t3 ...

Page 70

... VALID DATA CASE 2: BUSTMG pin = LOW min Next )** * 4T ARB 0***** if SLOW ARB = 0 from the trailing edge of nDS to the leading edge ARB from the trailing edge of nDS to ARB Page 70 DATASHEET Datasheet t13 t11 Note 2 t6 max units 40**** nS nS SMSC COM20022I ...

Page 71

... Low to nPULSE1 Low t5 Beginning of Last Bit Time to nTXEN High t6 RXIN Active Pulse Width t7 RXIN Period t8 RXIN Inactive Pulse Width Note: Use Only 2.5 Mbps Figure 8.13 - Normal Mode Transmit or Receive Timing (These signals are to and from the hybrid) SMSC COM20022I Parameter Page 71 DATASHEET t5 ...

Page 72

... Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM t10 t12 t11 Parameter Page 72 DATASHEET Datasheet t13 t8 LAST BIT (400 nS BIT TIME) min typ max units - 200* nS 400 100* nS 100* nS 200 -25 650 750 nS 450 550 nS 10 200* nS 400 SMSC COM20022I ...

Page 73

... High to Next nINTR Low Note period of external XTAL oscillation frequency. XTL Note**: T is period of Data Rate (i.e. at 2.5 Mbps Note***: When the power is turned on measured from stable XTAL oscillation after V DD Figure 8.16 SMSC COM20022I t2 t3 1.0V min -200 + - - TTL Input Timing on XTAL1 Pin ...

Page 74

... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM t20 t19 t26 t21 t4 t1 t24 t25 t15 t11 t16 t12 t14 t9 t8 VALID - DMA Timing (Intel Mode 80XX) Page 74 DATASHEET Datasheet t19 t20 t7* t24 t25 t13 t18 t17 VALID SMSC COM20022I ...

Page 75

... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Datasheet nCS t10 nREFEX t3 DREQ t2 nDACK TC DIR nDS Write LOW-POINTER when DMAEN=1 DATA (D15-D0) Note measured from the latest active timing among TC, Write/Read. Figure 8.18 SMSC COM20022I t20 t19 t26 t21 t4 t1 t24 t25 t15 t16 VALID t11 t22 t23 ...

Page 76

... Page 76 DATASHEET Datasheet MAX UNIT NOTE 5Tarb Note 1 +40ns 40 ns Note Note 4 8Txtl Note 2 +40ns 16Txtl +40ns 40 ns Note Note Note Note Note 4 Note 4 Note 4 ns Note 4,5 ns Note 1,4 Note 1,4,5 ns Note 4 ns Note Note 4 ns Note 4 Note 2 SMSC COM20022I ...

Page 77

... At MOTOROLA MODE, write signal is nDS when DIR is Low and the read signal is nDS when DIR is High. 5. Conditions of CASE1W, CASE2W, CASE1R and CASE2R are shown below; CASE1W : BUSTMG pin = High CASE2W : BUSTMG pin = Low CASE1R : BUSTMG pin = High and RBUSTMG bit = 0 CASE2R : BUSTMG pin = Low or RBUSTMG bit = 1 SMSC COM20022I Page 77 DATASHEET Revision 09-27-07 ...

Page 78

... Page 78 DATASHEET Datasheet REMARK Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity (Assemblers) Coplanarity (Test House) SMSC COM20022I ...

Page 79

... Setting the EF bit will change the minimum disable time to always be more than 200nS even if the Data Rate is 10Mbps . This is done by changing the clock which is supplied to the Interrupt Disable logic. The frequency of this clock is always 20MHz even if the data rate is 10Mbps. SMSC COM20022I Page 79 DATASHEET ...

Page 80

... Setting the EF bit will cause the TA/RI bit to return to High upon release of the internal pulse signal for setting the TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 10.1 on the following page. Revision 09-27-07 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM Page 80 DATASHEET Datasheet SMSC COM20022I ...

Page 81

... This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft reset. The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in the Configuration register. This solution is Enabled/Disabled by the EF bit. SMSC COM20022I Tx/Rx completed prohibition period ...

Page 82

... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM LS688x nG 12 bit Comparator P Q I/O Address Seeting (DIP P=Q 12 LS245x A 16 bit Transceiver DIR 3 Schmitt-Trigger Open-Collector Page 82 DATASHEET Datasheet COM2002I nCS D15-D0 nRD nWR A2-A0 nINTR nIOCS16 DREQ nDACK TC nREFEX nRESET SMSC COM20022I ...