COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 60

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

Revision 09-27-07
nIOCS16
AD0-AD2,
D3-D15
nWR
nCS
ALE
nRD
Figure 8.2
Note 1:
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
*
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
T
T
T
T
t10
t11
t12
t13
t14
t15
opr
ARB
ARB
ARB
t8
t9
t1
t2
t3
t4
t5
t6
t7
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
Previous Value
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
- Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
should be doubled when considering back-to-back COM20022 cycles.
Data Register requires a minimum of 5T
leading edge of the next nRD.
Data Register requires a minimum of 5T
leading edge of nRD.
nRD High to Data High Impedance
Cycle Time (nRD Low to Next Time Low)
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nRD Low
nRD Low to Valid Data
ALE High Width
ALE Low Width
nRD Low Width
nRD High Width
nWR
nIOCS16 Hold Delay from ALE Low
nIOCS16 Output Delay from ALE Low
Address Setup to ALE Low
Address Hold from ALE Low
MUST BE: BUSTMG pin = HIGH and RBUSTMG bit = 0
opr
t9
to nRD Low
if SLOW ARB = 1
t1
VALID
opr
t3
if SLOW ARB = 0
DATASHEET
t13
t14
t4
t2,
Parameter
Note 3
t5
Invalid
t15
Page 60
t6
ARB
ARB
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
from the trailing edge of nRD to the
from the trailing edge of nWR to the
t10
t11
VALID DATA
Valid Value
4T
min
20
10
10
10
15
ARB
20
20
60
20
20
0
t8
0
*
max
40
40
20
t7
Note 2
units
t12
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
SMSC COM20022I
Datasheet