COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 41

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I
2,1,0
BIT
7-0
BIT
7-3
Address 7-0
Reserved
Sub Address 2,1,0
BIT NAME
BIT NAME
A7-A0
SWAP
SUBAD
2,1,0
SYMBOL
SYMBOL
Table 6.7 - Address Pointer Low Register
Table 6.8 - Sub Address Register
DATASHEET
These bits are undefined.
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by writing
the Configuration Register.
These bits hold the lower 8 address bits which provide the
addresses to RAM.
When 16 bit access is enabled, (W16=1), A0 becomes the SWAP
bit. Swap bit is undefined after a hardware reset. The swap bit
must be set before W16 bit is set to “1”. The swap bit is used to
swap the upper and lower data byte. The swap bit influences
both CPU cycle and DMA cycle. See Table Below.
Intel 80xx Mode
(RD, WR Mode)
Motorola 68xx Mode
(DIR, DS Mode)
Detected Host Interface
0
0
0
0
1
1
1
1
Page 41
Mode
SUBAD1
0
0
1
1
0
0
1
1
DESCRIPTION
DESCRIPTION
SUBAD0
0
1
0
1
0
1
0
1
Swap Bit
1
0
1
0
Register
Tentative ID \ (Same
Node ID
Setup 1
Next ID
Setup 2
Bus Control
DMA Count
Reserved
D15-D8
Even
Even
Odd
Odd
Pin
\ as in
/ Config
/ Register)
Revision 09-27-07
D7-D0 Pin
Even
Even
Odd
Odd