MC68MH360RC25L Freescale Semiconductor, MC68MH360RC25L Datasheet - Page 92

• Manufacturer Part Number: MC68MH360RC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360RC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Since the SIMODE register defaults to 0x0000_0000, a typical application may set these
bits as follows:
Step 2: Initialize the SICR (SI clock route) register. The SICR register is defined on page
7-86 of the MC68360 User’s Manual and page 16-121 of the MPC860 User’s Manual.
Table 6-2 shows the SICR bit settings.
As the SICR register defaults to 0x0000_0000, a typical application may set these bits as
follows:
Step 3: Configure port A for TDMa and/or TDMb signals, L1TXDx, L1RXDx, L1TCLKx,
and L1RCLKx. For more information on port A, see page 7-358 of the MC68360 User’s
Manual and page 16-455 of the MPC860 User’s Manual.
The following setting enables TDMa and TDMb, and selects both L1TCLKx and
L1RCLKx pins. Note that only L1RCLKx is required if common clocking is selected by
the CRTx bit in the SIMODE register.
Step 4: Configure port B for TDMa and/or TDMb signals, L1CLKOx and L1ST1, 2, 3, and/
or 4. For more information on port B, see page 7-363 of the MC68360 User’s Manual and
page 16-460 of the MPC860 User’s Manual.
The following setting enables both L1CLKOx and all L1STx strobes. Note that the L1STx
functions are repeated on port C and should only be configured on one port.
GRx
SCx
RxCSx
TxCSx
SIMODE.CRTa = 1;
SIMODE.RFSDa = 1;
SIMODE.TFSDa = 1;
SICR.SC1 = 1;
PAPAR = 0xA5F0;
PADIR = 0x00F0;
PBPAR = 0xFC00;
PBDIR = 0x0C00;
Name
Freescale Semiconductor, Inc.
No. of Bits
For More Information On This Product,
1
1
3
3
Table 6-2. SICR Bit Settings
Go to: www.freescale.com
Support SCCx grant mode
Connect SCCx to TDM or NMSI
Connect SCCx receive to a clock
Connect SCCx transmit to a clock
QMC Supplement
/* common syncs & clocks */
/* receive frame sync = 1 clock delay */
/* transmit frame sync = 1 clock delay */
/* SCC1 is TDM */
/* init port A pin assignment register */
/* init port A data direction register */
/* init port B pin assignment register */
/* init port B data direction register */
Description
0
1
X - as SCx = 1
X - as SCx = 1
Setting