MC68MH360RC25L Freescale Semiconductor, MC68MH360RC25L Datasheet - Page 39

• Manufacturer Part Number: MC68MH360RC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360RC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 2-2 describes the fields in the time slot assignment table for receive.
Table 2-3 describes the fields in the time slot assignment table for transmit.
V
W
Tx channel
pointer
Mask(0–7)
V
W
Rx channel
pointer
Mask(0–7)
Name
Field
Table 2-3. Time Slot Assignment Table Entry Fields for Transmit Section
Table 2-2. Time Slot Assignment Table Entry Fields for Receive Section
Valid bit—The valid bit indicates whether this time slot is valid.
0 Logic 1 is transmitted. If the Tx signal of the TDM interface is programmed to be an open drain
1 Data is transmitted from its associated buffer in combination with the mask bit settings.
Wrap bit—The wrap bit identifies the last entry in TSATTx.
0 This is not the last time slot in the frame.
1 The RISC processor wraps around and handles time slot 0 or the first 8 bits of data in the SCC in
This 6-bit field of the TSATTx entry identifies the data channel routed to this time slot. The actual
channel pointer is 12 bits long, and contains the starting address of the channel-specific parameter
area (address of TBASE). The 6 most-significant bits are taken from the TSATTx channel pointer
field, and the 6 least-significant bits are always internally set to zero. For the MH360 the most-
significant bit must be set to zero, as the addressing range is 2 Kbytes.
Mask bits—Identifies the valid bits in this time slot for subchanneling support. For 8-bit resolution, all
mask bits should be set to 1. For a valid channel with an unmasked bit (1), the bit position is filled
according to the protocol. A valid channel with a masked bit (0) transmits a logic high (1).
Valid bit—The valid bit indicates whether this time slot is valid.
0 The data in this 8-bit time slot is totally ignored and not written to any buffer.
1 The data in this 8-bit time slot is valid and written to the current buffer, pointed to by the channel
Wrap bit—Identifies the last entry in TSATRx.
0 This is not the last time slot in the frame.
1 The RISC processor wraps around and handles time slot 0 or the first 8 bits transferred from the
This 6-bit field of the TSATRx entry identifies the data channel routed to this time slot. The actual
channel pointer is 12 bits long, and contains the starting address of the channel-specific parameter
area (address of RBASE). The 6 most-significant bits are taken from the TSATRx channel pointer
field, and the 6 least-significant bits are always internally set to zero. For the MH360, the most-
significant bit must be set to zero, as the addressing range is 2 Kbytes.
Mask bits—These 8 bits identify the valid bits in this time slot for subchanneling support. For 8-bit
resolution, all mask bits should be set to 1. Any unmasked bit (1) is processed in the receiver for a
valid time slot. Any masked bit (0) is ignored by the receiver for a valid channel and no bit counter is
affected.
output (port B programming), other devices can transmit on nonvalid time slots.
the next request. The next request is identified by a frame synchronization pulse.
pointer entry, after protocol processing (e.g. zero deletion in HDLC). Individual bits can be
masked out as described later.
TSA in the next request. The next request is identified by a frame synchronization pulse.
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 2. QMC Memory Organization
Go to: www.freescale.com
Description
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