MC68MH360RC25L Freescale Semiconductor, MC68MH360RC25L Datasheet - Page 47

• Manufacturer Part Number: MC68MH360RC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360RC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

2.4.1.2 TSTATE—Tx Internal State (HDLC)
TSTATE defines the internal transmitter state. The high byte of TSTATE defines the
function code/address type and the Motorola/Intel bit. Bit 3 (or bit 28 for the 68360) should
always be set to 1. Figure 2-8 shows the TSTATE register for HDLC operation.
For the MH360, TSTATE should be host-initialized to 0x3800_0000 before enabling the
channel—function code 8. Table 2-6 describes the TSTATE fields for the MH360 with
boldfaced parameters to be initialized by the user.
For the 860MH, TSTATE should be host-initialized to 0x3000_0000 before enabling the
channel—AT = 0. Note that for the 860MH, bit 4 should always be zero as only bits 5–7
map to AT[1–3]. Table 2-7 describes the TSTATE fields for the 860MH with boldfaced
parameters to be initialized by the user.
10–11
12–15
0–1
2
3
4–7
Field
Field
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
—
—
MOT
FC[3–0]
—
NOF
Name
Name
Table 2-5. CHAMR Field Descriptions (HDLC) (Continued)
Table 2-6. TSTATE Field Descriptions for MH360 (HDLC)
Reserved
Number of flags—Defines the minimum number of flags before frames. However, even if
NOF = 0, at least one flag is transmitted before the first frame. See the description of the IDLM
bit for more information.
0
1
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
Function code—This field contains the function code for the transmitter DMA channel for data
buffers in external memory (transmit buffers). Function codes are needed by the memory
controller to decode a correct memory cycle and activate the correct handshaking.
Freescale Semiconductor, Inc.
Figure 2-8. TSTATE—Tx Internal State (HDLC)
For More Information On This Product,
0
0
Chapter 2. QMC Memory Organization
1
0
Go to: www.freescale.com
2
1
MOT
3
4
Description
Description
FC[3–0]/ AT[1–3]
5
6
7