MC68MH360RC25L Freescale Semiconductor, MC68MH360RC25L Datasheet - Page 49

• Manufacturer Part Number: MC68MH360RC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360RC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

2.4.1.4 RSTATE—Rx Internal State (HDLC)
Host-initialized to 0x3900_0000 before enabling the channel or after a fatal error (that is,
global overrun, busy) or after a STOP Rx command.
The high byte of RSTATE defines the function code/address type and the Motorola/Intel bit.
Bit 3 (or bit 28 for the 68360) should always be set to 1. Figure 2-10 shows the RSTATE
register for HDLC operation.
For the MH360, RSTATE should be host-initialized to 0x3900_0000 before enabling the
channel—function code 9. Table 2-8 describes the RSTATE fields for the MH360 with
boldfaced parameters to be initialized by the user.
For the 860MH, RSTATE should be host-initialized to 0x3100_0000 before enabling the
channel—AT = 1. Note that for the 860MH, bit 4 should always be zero as only bits 5–7
map to AT[1–3]. Table 2-9 describes the RSTATE fields for the 860MH with boldfaced
parameters to be initialized by the user.
0–1
2
3
4–7
Field
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
—
—
MOT
FC[3–0]
Name
Table 2-8. RSTATE Field Descriptions for MH360 (HDLC)
Figure 2-10. RSTATE—Rx Internal State
Freescale Semiconductor, Inc.
0
1
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
Function code—This field contains the function code for the transmitter DMA channel for
data buffers in external memory (transmit buffers). Function codes are needed by the
memory controller to decode a correct memory cycle and activate the correct handshaking.
For More Information On This Product,
0
0
Chapter 2. QMC Memory Organization
1
0
Go to: www.freescale.com
2
1
MOT
3
4
Description
FC[3–0]/ AT[1–3]
5
6
(HDLC)
7