MC68MH360RC25L Freescale Semiconductor, MC68MH360RC25L Datasheet - Page 147

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MC68MH360RC25L

Manufacturer Part Number
MC68MH360RC25L
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68MH360RC25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
C.3.1.2 Deactivation Procedure
When the clock-master S/T interface is deactivated, the QUICC32 receives an interrupt
indicating the deactivation status (IRQ3 —register NR3 bit 3— meaning Info 0 of
Figure C-9 has been received). Then, if another S/T interface is active, its TCLK signal
must be selected to become the clock master; otherwise, the QUICC32 can select the BRG
to be the clock master.
As shown in Figure C-9, the TCLK signal is disabled about 72.8 s after the interruption.
Therefore, the QUICC32 has 72.8 s to react to the IRQ and to select another clock master.
Figure C-9. Timing Diagram for a Deactivation (Always Initiated by the NT)
Time
1: 500 ms (= 2 S/T Frames x 250 ms)
2: 72.8 ms (= 14 bit x 5.2 ms)
Appendix C. Connecting ISDN Multiple S/T or U Interfaces to QUICC32
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
TCLK
Disabled
IRQ3
(Rx Info 0)
TE
TX
RX
RX
TX
Info 3
Info 4
Info 0
Info 0
RX
RX
TX
TX
(Rx Info 0)
NT
IRQ3

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