MC68MH360RC25L Freescale Semiconductor, MC68MH360RC25L Datasheet - Page 66

• Manufacturer Part Number: MC68MH360RC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360RC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Field
0–3
4
5
6
7
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Name
—
IQOV
GINT
GUN
GOV
Reserved
Interrupt table (interrupt queue) overflow
0 No interrupt table overflow has occurred.
1 An overflow condition in the circular interrupt table occurs (and an interrupt request is
This entry is cleared by the software immediately after entering the interrupt routine. When this
occurs, the last interrupt is lost and not overwritten on the first entry.
Global interrupt
0 No global interrupt has occurred.
1 This flag indicates that at least one new entry in the circular interrupt table has been generated
The user must make sure that no more valid interrupts are pending in the interrupt table after
clearing the GINT bit, before performing the RTE to avoid deadlock. This procedure ensures that
no pending interrupts exist in the queue.
Global transmitter underrun
0 No global transmitter underrun has occurred.
1 This flag indicates that an underrun occurred in the SCC’s transmitter FIFO. This error is fatal
After initializing all the individual channels, the host may resume transmitting. If enabled in the
SCCM, an interrupt request is generated when GUN is set. The host may clear GUN by writing 1
to its location in the SCCE.
Global receiver overrun
0 No global receiver overrun has occurred.
1 This flag indicates that an overrun occurred in the SCC’s transmitter FIFO. This error is fatal
After initializing all the individual channels, the host may resume receiving. If enabled in SCCM,
an interrupt request is generated when GOV is set. The host may clear GOV by writing 1 to its
location in the SCCE.
generated). This condition occurs if the RISC processor attempts to write a new interrupt entry
into an entry that was not handled by the host. Such an entry is identified by V = 1.
by the QMC. The host clears GINT by writing a 1 to its location in SCCE. After clearing it, the
host reads the next entry from the circular interrupt table, and starts processing a specific
channel’s exception.
since it is unknown which channel(s) are affected. Following the assertion of the GUN bit in the
SCCE, the QMC stops transmitting data on all channels. The TDM Tx line goes into idle mode.
This error affects only the transmitter; the receiver continues to work.
since it is unknown which channel(s) are affected. Following the assertion of the GOV bit in the
SCCE, the QMC stops receiving data on all channels. Data is no longer written to memory.
This error affects only the receiver; the transmitter continues to work.
Freescale Semiconductor, Inc.
Table 4-1
For More Information On This Product,
0
Figure 4-2. SCC Event Register
.
SCC Event Register Field Descriptions
1
Go to: www.freescale.com
2
QMC Supplement
3
IQOV
Description
4
GINT
5
GUN
6
GOV
7