MC68MH360RC25L Freescale Semiconductor, MC68MH360RC25L Datasheet - Page 23

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MC68MH360RC25L

Manufacturer Part Number
MC68MH360RC25L
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68MH360RC25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
The following example shows how an MC68MH360 can implement the BRI using only one
SCC, leaving SCC3 and SCC4 available to run other protocols such as frame relay over
HDLC and another Ethernet link, on SCC1, to the LAN. The QMC protocol allows all three
channels B1, B2, and D to be routed to SCC2 using the TSA. The first byte (B1) is routed
to logical channel 1, the second byte (B2) to logical channel 2, and the third byte to logical
channel 3, of which only the first 2 bits represent the D channel as illustrated in Figure 1-4
and Figure 1-5. This routing is defined in the QMC time slot assignment tables. The first
advantage of the QMC protocol is that it releases SCCs to run other protocols. The second
advantage is highlighted in the next example.
Ethernet
Figure 1-3. Internal Routing for Ethernet-to-BRI Bridge Using MC68EN360
BRI ISDN
SCC1
NMSI
E
Freescale Semiconductor, Inc.
For More Information On This Product,
B1
SCC2
TSA
B1
Go to: www.freescale.com
B2
Chapter 1. Overview
SCC3
B2
Memory
EN360
D
SCC4
D
SMC1
SMC2
NMSI
U
UART

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