MC68MH360RC25L Freescale Semiconductor, MC68MH360RC25L Datasheet - Page 65

• Manufacturer Part Number: MC68MH360RC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360RC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

4.1.1 Global Underrun (GUN)
The QMC performs the following actions when it detects a GUN event:
4.1.2 Global Overrun (GOV) in the FIFO
A global overrun affects all channels operating from an SCC. Following GOV, the QMC
performs the following:
4.1.3 Restart from a Global Error
The last two bullets in the above two sections describe the only steps necessary for re-
initialization. The transmit and receive sections must be restarted individually for each
separate logical channel.
For details about initialization, see Chapter 6, “QMC Initialization.”
4.2 SCC Event Register (SCCE)
The QMC’s SCCE is a word-length register used to report events and generate interrupt
requests. See Figure 4-2 and Table 4-1 for SCCE field descriptions. For each of its flags, a
corresponding programmable mask/enable bit in the SCCM determines whether an
interrupt request is generated. If a bit in the SCCM register is zero, the corresponding
interrupt flag does not survive, and the CPM does not proceed with its usual interrupt
handling. If a bit in the SCCM is set, the corresponding interrupt flag in the SCCE survives,
and the SCC event bit is set in the CPM interrupt-pending register. See Figure 4-3 for
SCCM assignments.
• Transmits an abort sequence of minimum sixteen 1’s in each time slot.
• Generates an interrupt request to the host (if enabled) and sets the GUN bit in the
• Stops reading data from buffer.
• Sends IDLEs or FLAGs in all time slots depending on channel mode settings until
• Updates the RSTATE register to prevent further reception on this channel. Bit 20 in
• Generates an interrupt request to the host (if enabled) and sets the GOV bit in the
• Stops writing data to all channel’s buffers.
• Waits for host to initialize all the receiving channels by setting first the ZDSTATE
SCCE register.
the host does the following:
Host initializes all transmitting channels and time slots by preparing all buffer
descriptors for transmission (R bits are set) and setting the POL bit. No other re-
initialization is needed.
the RSTATE register indicates that the receiver is stopped.
SCCE.
followed by the RSTATE to their initial values.
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Chapter 4. QMC Exceptions