MC68MH360RC25L Freescale Semiconductor, MC68MH360RC25L Datasheet - Page 133

• Manufacturer Part Number: MC68MH360RC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360RC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Q: My understanding is that the MH360 could not support the SS-7 microcode. Is this
A: The 860MH will not support SS-7 over the multiplexed (QMC) channels. If SS-7 is
Q: What is the CPM’s maximum CPU bus utilization when running two 2-Mbps QMC
A: For 64 channels (two E1 lines), two 2-Mbps full duplex means 8 Mbps of aggregate
Q: Is the 860MH pin compatible with the 860DH?
A: Yes, it is pin compatible.
Q: Are BISYNC and Centronics still removed from the 860MH as they are with the
A: No, Centronics and Bisync are both supported on the 860MH.
Q: How is time slot 0 identified on an SCC? Is an external sync required?
A: The TSA identifies time slot 0. A sync pulse must be provided to the TSA at the
Q: What does the larger dual-ported RAM on the 860MH provide?
A: The larger dual-ported RAM means that up to 64 QMC channels may be supported.
• A hybrid approach runs a single line of up to 64 multiplexed time slots to two
also true of the 860MH?
to be run, it must be run over its own dedicated SCC. However, by using the time
slot assigner, the traffic from this SCC could be routed over the same E1 or T1 as the
other multiplexed HDLC channels.
For example, one channel of an E1 could be routed to an SCC running SS-7, and the
other 31 channels to an SCC running QMC. Thus, the number of SS-7 channels
allowed is limited to the number of SCCs (that is, at most 4).
channels?
traffic. Factoring in a large margin for buffer descriptor accesses bumps this 8 Mbps
up to 10 Mbps. The 10 Mbps of traffic translates to 0.3 megatransfers of 32 bits each
requiring only 1.5 MHz out of a 50-MHz bus (assuming a 5 wait-state memory). A
similar calculation for Ethernet would account for higher data traffic and fewer
descriptor accesses.
MH360?
beginning of a frame.
It also provides more buffer descriptor area needed for the higher serial performance
at higher speeds.
separate SCCs, each with its own set of parameters. Normally this would route
32 time slots to each SCC. This would have the benefit of doubling your effective
FIFO depth, allowing greater system design flexibility.
Freescale Semiconductor, Inc.
For More Information On This Product,
Appendix B. Frequently-Asked Questions
Go to: www.freescale.com