MC68MH360RC25L Freescale Semiconductor, MC68MH360RC25L Datasheet - Page 63

• Manufacturer Part Number: MC68MH360RC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360RC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Chapter 4
QMC Exceptions
40
40
QMC interrupt handling involves two principle data structures—the SCC event register
(SCCE) and the circular interrupt table. Figure 4-1 illustrates the circular interrupt table.
INTBASE (interrupt base) points to the starting location of the queue in external memory,
and INTPTR (interrupt pointer) marks the current empty position available to the RISC
processor. Both pointers are host-initialized global QMC parameters; see Table 2-1. The
entry whose W (wrap) bit is set to 1 marks the end of the queue. When one of the QMC
channels generates an interrupt request, the RISC processor writes a new entry to the queue.
In addition to the channel’s number, this entry contains a description of the exception. The
V (valid) bit is then set and INTPTR is incremented. When INTPTR reaches the entry with
W = 1, INTPTR is reset to INTBASE.
An interrupt is written to the interrupt table only if it survives a mask with the INTMASK
(interrupt mask) register. Following a write to the queue, the QMC protocol updates the
SCC event register (SCCE) according to the type of exception.
SOFTWARE POINTER
Figure 4-1. Circular Interrupt Table in External Memory
INTBASE
INTPTR
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Chapter 4. QMC Exceptions
V = 1
V = 1
V = 1
V = 1
V = 0
V = 0
V = 0
V = 0
V = 0
V = 0
W = 0
W = 0
W = 0
W = 0
W = 0
W = 1
W = 0
W = 0
W = 0
W = 0
16 Bits
Interrupt Flags
Interrupt Flags
Interrupt Flags
Interrupt Flags
X
X
X
X
X
X