EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 97
EZ80190AZ050SG
Manufacturer Part Number
EZ80190AZ050SG
Description
IC WEBSERVER 8 BIT 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3866
EZ80190AZ050SG
EZ80190AZ050SG
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80190AZ050SG
Manufacturer:
ZiLOG
Quantity:
135
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PS006614-1208
Baud Rate
Generator
responds by sending data to the master via the master’s MISO signal. The result is a full-
duplex transmission, with both data out and data in synchronized with the same clock sig-
nal. The byte transmitted is replaced by the byte received, eliminating the requirement for
separate transmit-empty and receive-full status bits. A single status bit, SPIF, is used to
signify that the I/O operation is completed, see
SPI1_SR =
The SPI is double-buffered on read, but not on write. If a write is performed during data
transfer, the transfer occurs uninterrupted, and the write is unsuccessful. This condition
causes the WRITE COLLISION (WCOL) status bit in the SPIx_SR register to be set.
After a data byte is shifted, the SPI flag bit (SPIF) of the SPIx_SR register is set.
In SPI MASTER mode, the SCK pin is an output. It idles High or Low, depending on the
CPOL bit in the SPIx_CTL register, until data is written to the shift register. When data is
Divide by Two
SPIx_SR Register
SPI Control
msb
BBh
) on page 90.
Internal Address Databus
8-Bit Shift Register
Read Data Buffer
Figure 15. SPI Block Diagram
Clock Logic
SPIx_CTL Register
lsb
SPI Status Register
Master
Master
Master
Slave
Slave
Slave
Control
Logic
Pin
Product Specification
Serial Peripheral Interface
(SPI0_SR =
Signal
Signal
Signal
MOSI
Signal
MISO
SCK
SS
B7h
eZ80190
,
87
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