EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 53

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

General-Purpose Input/Output
GPIO Overview
GPIO Operation
Table 12. GPIO Mode Selection
PS006614-1208
GPIO
Mode
1
2
Px_ALT2
Bits7:0
0
0
0
0
The eZ80190 device features 32 General-Purpose Input/Output (GPIO) pins. The GPIO
pins are assembled as four 8-bit ports—Port A, Port B, Port C, and Port D. All port signals
can be configured for use as either inputs or outputs. In addition, all of the port pins can be
used as vectored interrupt sources for the eZ80
GPIO operation is the same for all four GPIO ports (Ports A, B, C, and D). Each port fea-
tures eight GPIO port pins. The operating mode for each pin is controlled by four bits that
are divided between four 8-bit registers. These GPIO mode control registers are:
•
•
•
•
where, x can be A, B, C, or D, representing any of the four GPIO ports A, B, C, or D. The
mode for each pin is controlled by setting each register bit pertinent to the pin to be config-
ured. For example, the operating mode for Port B Pin 7 (PB7) is set by the values con-
tained in PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7].
The combination of the GPIO control register bits allows individual configuration of each
port pin for nine modes. In all modes, reading the Port x Data register returns the sampled
state, or level, of the signal on the corresponding pin.
port signal based upon these four register bits. After a RESET event, all GPIO port pins
are configured as standard digital inputs, with interrupts disabled.
Port x Data Register (Px_DR)
Port x Data Direction Register (Px_DDR)
Port x Alternate Register 1 (Px_ALT1)
Port x Alternate Register 2 (Px_ALT2)
Px_ALT1
Bits7:0
0
0
0
0
Px_DDR
Bits7:0
0
0
1
1
Bits7:0 Port Mode
Px_DR
0
1
0
1
Output
Output
Input from pin
Input from pin
®
CPU.
Table 12
General-Purpose Input/Output
lists the function of each
Product Specification
Output
0
1
High impedance
High impedance
eZ80190
43