EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 121
EZ80190AZ050SG
Manufacturer Part Number
EZ80190AZ050SG
Description
IC WEBSERVER 8 BIT 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3866
EZ80190AZ050SG
EZ80190AZ050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80190AZ050SG
Manufacturer:
ZiLOG
Quantity:
135
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PS006614-1208
Table 55. I
Bus Clock Speed
Bit
Reset
CPU Access
Note: W = Read Only.
Bit
Position
7
[6:3]
M
[2:0]
N
The I
quency of f
lowing equation.
In MASTER mode, the I
The use of two separately-programmable dividers allows the MASTER mode output fre-
quency to be set independently of the frequency at which the I
dividers are particularly useful in multimaster systems because the I
quency must be at least 10 times the frequency of the fastest master on the bus to ensure
that START and STOP conditions are always detected. By using two programmable clock
divider stages, a high sampling frequency can be ensured, while allowing the MASTER
mode output to be set to a lower frequency.
The I
2
C Clock Control Registers
2
2
C clocks are derived by the eZ80190 device’s system clock, which provides a fre-
C bus is defined for bus clock speeds up to 100 kbps (400 kbps in FAST mode).
Value
0
0000–
1111
000–111 I
sclk
. The I
W
Description
Reserved.
I
7
0
2
2
C clock divider scalar value.
C clock divider exponent.
2
C bus is sampled by the I
f
SCL
2
C clock output frequency on SCLx (f
W
6
0
f
SAMP
=
10 x (M+1) x 2
W
=
5
0
f
f
SCLK
SCLK
2
(I2C0_CCR = CCh, I2C1_CCR = DCh)
N
W
4
0
2
C block at the frequency f
N
W
3
0
W
2
0
2
scl
C bus is sampled. These
Product Specification
) is provided by:
2
W
1
0
C bus sampling fre-
I2C Serial I/O Interface
samp
W
0
0
in the fol-
111
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