EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 103

IC WEBSERVER 8 BIT 50MHZ 100LQFP

EZ80190AZ050SG

Manufacturer Part Number
EZ80190AZ050SG
Description
IC WEBSERVER 8 BIT 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80190AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3866
EZ80190AZ050SG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80190AZ050SG
Manufacturer:
ZiLOG
Quantity:
135
Part Number:
EZ80190AZ050SG
Manufacturer:
Zilog
Quantity:
10 000
Transferring Data
PS006614-1208
Data Validity
START and STOP Conditions
Byte Format
SDA Signal
SCL Signal
SDA Signal
SCL Signal
The data on the SDA line must be stable during the High period of the clock. The High or
Low state of the data line can only change when the clock signal on the SCL line is Low,
as displayed in
Within the I
STOP conditions, see
High indicates a START condition. A Low-to-High transition on the SDA line while SCL
is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to
be busy after the START condition. The bus is considered to be free at a defined time after
the STOP condition.
Every character transferred on the SDA line must be a single 8-bit byte. The number of
bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an
Start Condition
2
C bus protocol, unique situations arise which are defined as START and
Figure 17. START and STOP Conditions In I
Figure
S
Data Valid
Data Line
Stable
Figure 16. I
Figure
16.
17. A High-to-Low transition on the SDA line while SCL is
Data Allowed
Change of
2
C Clock and Data Relationship
Stop Condition
2
C Protocol
Product Specification
P
I2C Serial I/O Interface
93

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