EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 136

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

PS006614-1208
x_ADDR
MACC x DATA
MACC
2. MACC_xEND and MACC_yEND define the end of the linear address space for the x
3. MACC_xRELOAD and MACC_yRELOAD define the circular address to be used
An example of address indexing for a MACC calculation is displayed in
page 127. The first value is the address returned by the MACC_xSTART register, taken
from the x RAM memory location. The address increments linearly until the value is used
from the address returned by the MACC_xEND register. Instead of incrementing to the
next linear address, the next value is taken from the address returned by the
MACC_xRELOAD register. Incrementing recommences until the required number of
multiply-accumulate operations is completed, as defined by the value in the
MACC_LENGTH register.
FEh
FFh
02h
01h
00h
and y data, respectively. After either the x or y ending value is reached, the next
address is defined by MACC_xRELOAD or MACC_yRELOAD, respectively.
when either the x index counter or the y index counter reaches the ending value for the
linear address space.
{RAM_ADDR_U[7:0], ADDR[15:0]}
X_ADDR[7:0]
DDFFh
DDFDh
X[15:8]
DC05h
DC03h
DC01h
ADDRESS
X_DATA[15:0]
DDFCh
DDFEh
DC04h
DC02h
DC00h
X[7:0]
To the Mulitply-Accumulator
Figure 23. MACC RAM Block Diagram
To the eZ80
®
MACC y DATA
Y_ADDR[7:0]
CPU
DFFDh
DATA[7:0]
Y[15:8]
DFFFh
DE05h
DE03h
DE01h
Y_DATA[15:0]
DFFCh
DFFEh
DE04h
DE02h
DE00h
Y[7:0]
Product Specification
y_ADDR
FEh
FFh
02h
01h
00h
MACC
Multiply-Accumulator
Figure 24
eZ80190
on
126