EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 139

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

PS006614-1208
MACC Length Register
Table 63. MACC Length Register
MACC
Table 64. MACC y DATA Starting Address Register
Bit
Position
[7:0]
MACC_xRELOAD
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
MACC_LENGTH
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
MACC_ySTART
The MACC_LENGTH register, listed in
pairs that are multiplied and accumulated for the MACC operation.
The MACC_ySTART register, listed in
MACC to read 16-bit values from the y DATA for performing its calculations.
y
DATA Starting Address Register
Value Description
00h–
FFh
Value Description
00h–
FFh
Value Description
00h–
FFh
R/W
R/W
7
0
7
0
The reload address for MACC RAM x DATA.
Total number of address pairs to be multiplied and
accumulated for the current MACC operation.
Starting address for the y DATA of MACC RAM.
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
Table
Table
R/W
R/W
4
0
4
0
64, defines the starting address for the
(MACC_LENGTH = E3h)
63, defines the total number of x and y data
R/W
R/W
3
0
3
0
(MACC_ySTART = E4h)
R/W
R/W
2
0
2
0
Product Specification
R/W
R/W
1
0
1
0
Multiply-Accumulator
R/W
R/W
0
0
0
0
eZ80190
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