EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 54

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

Table 12. GPIO Mode Selection (Continued)
PS006614-1208
GPIO
Mode
3
4
5
6
7
8
9
Px_ALT2
Bits7:0
0
0
0
0
1
1
1
1
1
1
1
1
GPIO Mode 1—
ten to the Port x Data register (Px_DR) is presented on the pin.
GPIO Mode 2—
tristated (high impedance). The value stored in the Port x Data register produces no effect.
As in all modes, a read from the Port x Data register returns the pin’s value. GPIO Mode 2
is the default operating mode following a RESET.
GPIO Mode 3—
ture an internal pull-up to the supply voltage. To employ the GPIO pin in open-drain
mode, an external pull-up resistor must connect the pin to the supply voltage. Writing a 0
to the Port x Data register outputs a Low at the pin. Writing a 1 to the Port x Data register
results in high-impedance output.
GPIO Mode 4—
ture an internal pull-down to the supply ground. To employ the GPIO pin in open-source
mode, an external pull-down resistor must connect the pin to the supply ground. Writing a
1 to the Port x Data register outputs a High at the pin. Writing a 0 to the Port x Data regis-
ter results in a high-impedance output.
GPIO Mode 5—
Px_ALT1
Bits7:0
1
1
1
1
0
0
0
0
1
1
1
1
Px_DDR
Bits7:0
The port pin is configured as a standard digital output pin. The value writ-
The port pin is configured as a standard digital input pin. The output is
The port pin is configured as open-drain I/O. The GPIO pins do not fea-
The port pin is configured as open-source I/O. The GPIO pins do not fea-
Reserved. This pin produces high-impedance output.
0
0
1
1
0
0
1
1
0
0
1
1
Bits7:0 Port Mode
Px_DR
0
1
0
1
0
1
0
1
0
1
0
1
Open-Drain output
Open-Drain I/O
Open source I/O
Open source output
Reserved
Interrupt—dual edge triggered
Port A or B—input from pin, high-impedance output.
Port C or D—alternate function controls port I/O.
Port A or B—input from pin, high-impedance output.
Port C or D—alternate function controls port I/O.
Interrupt—active Low
Interrupt—active High
Interrupt—falling edge triggered
Interrupt—rising edge triggered
General-Purpose Input/Output
Product Specification
Output
0
High impedance
High impedance
1
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
eZ80190
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