EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 116
EZ80190AZ050SG
Manufacturer Part Number
EZ80190AZ050SG
Description
IC WEBSERVER 8 BIT 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3866
EZ80190AZ050SG
EZ80190AZ050SG
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80190AZ050SG
Manufacturer:
ZiLOG
Quantity:
135
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PS006614-1208
Table 50. I
I
Table 51. I
I
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SLAX
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
DATA
2
2
C Control Register
C Data Register
The I
mitted or the data byte just received. In MASTER TRANSMIT or SLAVE TRANSMIT
modes, the msb of the byte is transmitted first. In MASTER RECEIVE or SLAVE
RECEIVE modes, the first bit received is placed in the msb of the register. After each byte
is transmitted, the I2Cx_DR register contains the byte that is present in the event of lost
arbitration.
The I2Cx_CTL register, listed in
interrupts and the master slave relationships on the I
When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when the IFLG
is set to 1. When IEN is cleared to 0, the interrupt line always remains Low.
2
2
C Extended Slave Address Registers
C Data Registers
2
C Data Register, listed in
Value Description
00h–
FFh
Value Description
00h–
FFh
R/W
R/W
Least significant 8 bits of the 10-bit extended slave address.
I
7
0
7
0
2
C data byte.
R/W
R/W
6
0
6
0
Table
Table 52
R/W
R/W
5
0
5
0
51, contains the data byte/slave address to be trans-
(I2C0_DR = CAh, I2C1_DR = DAh)
is a control register that is used to control the
R/W
R/W
4
0
4
0
(I2C0_xSAR = C9h, I2C1_xSAR = D9h)
R/W
R/W
2
3
0
3
0
C bus.
R/W
R/W
2
0
2
0
Product Specification
R/W
R/W
1
0
1
0
I2C Serial I/O Interface
R/W
R/W
0
0
0
0
106
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