EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 175
EZ80190AZ050SG
Manufacturer Part Number
EZ80190AZ050SG
Description
IC WEBSERVER 8 BIT 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3866
EZ80190AZ050SG
EZ80190AZ050SG
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Manufacturer
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Price
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Part Number:
EZ80190AZ050SG
Manufacturer:
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PS006614-1208
Bit
Position
2
IEF1
[1:0]
ZDI Read Register Low, High, and Upper
Table 93. ZDI Read Registers—Low, High and Upper
ZDI Read Memory Data Value Register
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
ZDI_RD_L,
ZDI_RD_H,
or
ZDI_RD_U
The ZDI register Read Only address space offers Low, High, and Upper functions, which
contain the value read by a read operation from the ZDI Read/Write Control register
(ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and only if the
instruction is read by a request from the ZDI Read/Write Control register. See
When a read is executed from the ZDI Read Memory Data Value register, listed in
Table
to by the program counter, PC, and the program counter is incremented. In Z80
the memory address is {MBASE, PC[15:0]}. In ADL mode, the memory address is
PC[23:0]. For more information regarding Z80 and ADL MEMORY modes, refer to
eZ80
data read. However, the ZDI register address does not increment automatically when this
®
94, the eZ80190 device fetches the data from the memory address currently pointed
CPU User Manual (UM0077). The program counter, PC, increments after each
Value Description
0
1
00b
Value Description
00h–
FFh
The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable
interrupts are disabled.
The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable
interrupts are enabled.
Reserved—must be 0.
R
7
0
Values read from the memory location as requested by the
ZDI Read Control register during a ZDI read operation. The
24-bit value is stored in {ZDI_RD_U, ZDI_RD_H,
ZDI_RD_L}.
R
6
0
ZDI_RD_U = 12h)
R
5
0
R
4
0
(ZDI_RD_L = 10h, ZDI_RD_H = 11h,
R
3
0
R
2
0
Product Specification
R
1
0
Zilog Debug Interface
R
0
0
Table
®
eZ80190
mode,
93.
165
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