EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 188

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

Table 111. Op Code Map—Fourth Byte After 0FDh, 0CBh, and dd
PS006614-1208
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
Notes:
Legend
First Operand
of Fourth
0
Nibble
Upper
Byte
d = 8-bit two’s-complement displacement.
1
Lower Nibble of 4th Byte
4
2
0,(IY+d)
BIT
6
3
Second Operand
Mnemonic
4
5
RES 0,
RES 2,
RES 4,
RES 6,
SET 0,
SET 2,
SET 4,
SET 6,
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
BIT 0,
BIT 2,
BIT 4,
BIT 6,
RLC
SLA
RL
6
Lower Nibble (Hex)
7
8
9
A
B
Product Specification
C
D
Op-Code Map
RES 1,
RES 3,
RES 5,
RES 7,
SET 1,
SET 3,
SET 5,
SET 7,
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
BIT 1,
BIT 3,
BIT 5,
BIT 7,
RRC
SRA
SRL
RR
E
eZ80190
F
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