EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 76
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EP20K100QC240-3
Manufacturer Part Number
EP20K100QC240-3
Description
IC APEX 20K FPGA 100K 240-PQFP
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K100QC240-3
Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
189
Number Of Gates
263000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1094
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K100QC240-3N
Manufacturer:
ALTERA
Quantity:
150
Part Number:
EP20K100QC240-3V
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
APEX 20K Programmable Logic Device Family Data Sheet
Note to
(1)
76
t
t
t
t
t
t
t
t
t
t
INSUBIDIR
INHBIDIR
OUTCOBIDIR
XZBIDIR
ZXBIDIR
INSUBIDIRPLL
INHBIDIRPLL
OUTCOBIDIRPLL
XZBIDIRPLL
ZXBIDIRPLL
Table 39. APEX 20KE External Bidirectional Timing Parameters
These timing parameters are sample-tested only.
Symbol
Tables 38
and 39:
Setup time for bidirectional pins with global clock at LAB adjacent Input
Register
Hold time for bidirectional pins with global clock at LAB adjacent Input
Register
Clock-to-output delay for bidirectional pins with global clock at IOE output
register
Synchronous Output Enable Register to output buffer disable delay
Synchronous Output Enable Register output buffer enable delay
Setup time for bidirectional pins with PLL clock at LAB adjacent Input
Register
Hold time for bidirectional pins with PLL clock at LAB adjacent Input
Register
Clock-to-output delay for bidirectional pins with PLL clock at IOE output
register
Synchronous Output Enable Register to output buffer disable delay with
PLL
Synchronous Output Enable Register output buffer enable delay with PLL
Parameter
Note (1)
Altera Corporation
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
Conditions